Independently accessed double-gate and tri-gate transistors

• US 8,399,922 B2
• Filed: 09/14/2012
• Issued: 03/19/2013
• Est. Priority Date: 09/29/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chang, Peter L. D., Doyle, Brian S.
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US13/620,282
• Publication Number:
  US 20130009248A1
• Time in Patent Office: 186 Days
• Field of Search: 257/338, 257/347, 257/331, 257/270, 257/287, 438/221
• US Class Current: 257/331
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET

Abstract

A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device.

Claims

1. An integrated circuit comprising:

a substrate;

a tri-gate transistor on the substrate having a body surrounded on three sides by a first metal gate; and

an independently accessed, double-gate transistor on the substrate having a body having two independent metal gates on opposite sides of the body.

2. The circuit defined by claim 1, wherein the body of the tri-gate transistor and the body of the independently accessed, double-gate transistor each comprise monocrystalline silicon.

3. The circuit defined by claim 2, including an insulating member disposed on the body of the independently accessed, double-gate transistor, between the independent metal gates.

4. The circuit defined by claim 3, wherein the insulating member comprises silicon nitride.

5. The circuit defined by claim 1, including a plurality of the trigate and the independently accessed, double-gate transistors, some of which are n channel transistors and others of which are p channel transistors.

6. The circuit defined by claim 5, wherein the bodies of the transistors comprise monocrystalline silicon.