Layout for multiple-fin SRAM cell

• US 8,399,931 B2
• Filed: 06/30/2010
• Issued: 03/19/2013
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy, Shen, Jeng-Jung
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US12/827,690
• Publication Number:
  US 20120001197A1
• Time in Patent Office: 993 Days
• Field of Search: 257/137, 257/204, 257/255, 257/288, 257/296, 257/369, 257/331, 257/499, 257/510, 257/622, 438/149, 438/187, 438257-258, 438/593, 365/230.5, 365/154, 365/174
• US Class Current: 257/369
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.

Claims

1. A static random access memory (SRAM) cell comprising:

a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include first and second adjacent fin active regions having a first spacing and a third fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing;

a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to form first and second inverters cross-coupled for data storage and at least one port for data access;

a first contact disposed between the first and second fin active regions, electrically contacting the two fin active regions; and

a second contact disposed on and electrically contacting the third fin active region.

2. The SRAM cell of claim 1, wherein the first and second fin active regions further include first and second epitaxy features formed on the first and second fin active regions, respectively.

3. The SRAM cell of claim 2, wherein the first and second epitaxy features are laterally merged together and the first contact is formed on the first and second epitaxy features laterally merged together.

4. The SRAM cell of claim 2, wherein the first and second epitaxy features include silicon germanium and are portions of p-type FinFETs.

5. The SRAM cell of claim 2, wherein the first and second epitaxy features include silicon carbide and are portions of n-type FinFETs.

6. The SRAM cell of claim 2, wherein the first and second epitaxy features include silicon having a raised structure higher than a gate dielectric layer of a gate stack.

7. The SRAM cell of claim 6, further comprising silicide features formed on the first and second epitaxy features and underlying the first contact.

8. The SRAM cell of claim 1, wherein:

the plurality of fin active regions each includes an epitaxy feature disposed on another portion of the fin active region extended from the semiconductor substrate;

an interface between the epitaxy feature and another portion of the fin active region; and

isolation features disposed laterally between the plurality of fin active regions, the interface is vertically below a top surface of the isolation features.

9. The SRAM cell of claim 1, the first contact further contacts another fin active region adjacent to the first and second fin active region with a spacing being equal to the first spacing.

10. The SRAM cell of claim 1, wherein the plurality of FinFETs include:

a first and second pull-up devices;

a first pull-down device configured with the first pull-up device to form a first inverter;

a second pull-down device configured with the second pull-up device to form a second inverter; and

a first and second pass-gate devices configured with the first and second inverters as a first port.

11. The SRAM cell of claim 10, further comprising:

a third pull-down device configured with the first pull-down device in parallel; and

a fourth pull-down device configured with the second pull-down device in parallel.

12. A semiconductor structure comprising:

first and second fin active regions extended from a semiconductor substrate and spaced away from each other with a first distance;

third and fourth fin active regions extended from the semiconductor substrate and spaced away from each other with a second distance greater than the first distance;

first and second epitaxy features formed on the first and second fin active regions, respectively, wherein the first and second epitaxy features are laterally merged together;

third and fourth epitaxy features formed on the third and fourth fin active regions, respectively, wherein the third and fourth epitaxy features are separated from each other;

a first contact disposed on the first and second epitaxy features merged together; and

a second contact disposed on the third epitaxy feature, wherein the second contact is spaced away from the fourth epitaxy feature and is not electrically connected to the fourth fin active region.

13. The semiconductor structure of claim 12, further comprising

an isolation feature disposed laterally between the first and second fin active regions;

and

an interface between the first epitaxy feature and the first fin active region, wherein the interface is below a top surface of the isolation feature.

14. The semiconductor structure of claim 12, further comprising a silicide feature between the third epitaxy feature and the third fin active region.

15. The semiconductor structure of claim 12, further comprising various n-type fin field-effect transistors (nFinFETs) and p-type fin field-effect transistors (pFinFETs) configured to form two cross-coupled inventers.

16. The semiconductor structure of claim 15, wherein:

the first contact is coupled to source/drain regions of two adjacent nFinFETs; and

the second contact is coupled to a source/drain region of a pFinFET.

17. The semiconductor structure of claim 15, wherein:

one of the first through fourth epitaxy features includes one of silicon, silicon germanium and silicon carbide; and

the semiconductor substrate includes silicon.