Dual-depth self-aligned isolation structure for a back gate electrode
First Claim
1. A semiconductor structure comprising:
- at least one stack of a buried insulator portion and a semiconductor portion located in a substrate;
a shallow trench isolation structure laterally surrounding each of said at least one stack;
a doped semiconductor back gate region located underneath said at least one stack; and
a deep trench isolation structure laterally contacting a sidewall of said doped semiconductor back gate region, wherein at least one pair of parallel sidewalls of said at least one stack is vertically coincident with a pair of parallel sidewalls of said doped semiconductor back gate region.
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Abstract
Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks.
16 Citations
11 Claims
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1. A semiconductor structure comprising:
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at least one stack of a buried insulator portion and a semiconductor portion located in a substrate; a shallow trench isolation structure laterally surrounding each of said at least one stack; a doped semiconductor back gate region located underneath said at least one stack; and a deep trench isolation structure laterally contacting a sidewall of said doped semiconductor back gate region, wherein at least one pair of parallel sidewalls of said at least one stack is vertically coincident with a pair of parallel sidewalls of said doped semiconductor back gate region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification