High performance sub-system design and assembly

• US 8,399,988 B2
• Filed: 06/30/2011
• Issued: 03/19/2013
• Est. Priority Date: 03/01/1999
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US13/174,317
• Publication Number:
  US 20110254001A1
• Time in Patent Office: 628 Days
• Field of Search: 257/202, 257/676, 257/738, 257/777, 257/E25.013, 438106-108
• US Class Current: 257/738
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry.

Claims

1. A chip package comprising:

a first integrated circuit chip;

a second integrated circuit chip over said first integrated circuit chip, wherein said second integrated circuit chip comprises one of a driver and a receiver, and also comprises an electrostatic discharge protection circuit connected to a terminal of said driver/receiver; and

a metal bump having a bottom end contacting a first pad of said first integrated circuit chip and a top end contacting a second pad of said second integrated circuit chip, wherein there is no metal bump between a third pad of said second integrated circuit chip and said first integrated circuit chip, wherein said third pad is connected to said terminal of said driver/receiver.

2. The chip package of claim 1, wherein said first integrated circuit chip comprises a fourth pad vertically under said third pad.

3. The chip package of claim 1, wherein no test interface circuit in said first integrated circuit chip is in a signal path between an internal circuit of said first integrated circuit chip and said first pad.

4. The chip package of claim 1, wherein no test interface circuit in said first integrated circuit chip is in a first signal path between a first internal circuit of said first integrated circuit chip and said first pad, and no test interface circuit in said second integrated circuit chip is in a second signal path between a second internal circuit of said second integrated circuit chip and said second pad.

5. The chip package of claim 1, wherein said metal bump comprises a solder.

6. The chip package of claim 1 further comprising a wire bond on a fourth pad of said first integrated circuit chip.

7. The chip package of claim 1 further comprising a module under said first integrated circuit chip, wherein said module is connected to a fourth pad of said first integrated circuit chip.