Wafer level contactor

• US 8,400,176 B2
• Filed: 08/18/2009
• Issued: 03/19/2013
• Est. Priority Date: 08/18/2009
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Arkin, Brian J., Sporck, Alistair Nicholas
• Primary Examiner(s): Vazquez, Arleen M
• Application Number:
  US12/543,386
• Publication Number:
  US 20110043233A1
• Time in Patent Office: 1,309 Days
• Field of Search: 324/754.07, 324/756.03, 324/756.05, 324/755.03, 324/750.3
• US Class Current: 324/756.03
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/52 Testing for short-circuits, leakage current or ground faults
• CPC Class Codes: G01R 31/54 Testing for continuity

Abstract

A probe card assembly can include a plurality of probes disposed on a substrate and arranged to contact terminals of a semiconductor wafer. Switches can be disposed on the probe card assembly and provide for selective connection and disconnection of the probes from electrical interconnections on the probe card assembly.

Claims

1. A probe card assembly for testing semiconductor dies, the probe card assembly comprising:

a rigid substrate;

an electrical interface to a tester;

sets of probes disposed on the substrate, each said set of probes comprising multiple probes arranged to contact multiple terminals of one of the semiconductor dies, wherein each set of probes is arranged to contact the terminals of a different one of the semiconductor dies;

a plurality of switches interconnecting ones of the probes to electrical interconnections to the electrical interface;

an overcurrent detector means for detecting excessive current at one of the terminals of a failed one of the semiconductor dies; and

a means for controlling, in response to the overcurrent detector means detecting the excessive current at the one of the terminals of the failed one of the semiconductor dies, the switches to disconnect all of the multiple probes in the set of probes corresponding to the terminals of the failed one of the semiconductor dies.

2. The probe card assembly of claim 1, further comprising means for accepting a map of known failed ones of the plurality of semiconductor dies via the electrical interface, wherein the means for controlling the switches further disconnects all of the probes corresponding to the terminals of the known failed ones of the plurality of semiconductor dies from the electrical interconnections.

3. The probe card assembly of claim 1, further comprising means for performing a continuity check of electrical paths between the electrical interface and the probes.

4. The probe card assembly of claim 1, further comprising a memory configured to store fault information identifying the failed one of the plurality of semiconductor devices.

5. The probe card assembly of claim 1, further comprising a communication interface configured to communicate fault information between the probe card assembly and a tester, the fault information comprising identification of the failed one of the plurality of semiconductor devices.

6. The probe card assembly of claim 1, wherein the electrical interconnections comprise a power bus and a signal bus.

7. The probe card assembly of claim 1, further comprising a power converter configured to perform a power conversion between an input power provided to the probe card assembly and power supplied to the semiconductor dies.

8. The probe card assembly of claim 1, wherein the switches are selected from the group consisting of:

an electromechanical relay, a transistor, a thyristor, and a photo coupled field effect transistor.

9. A probe card assembly for testing a plurality of semiconductor devices disposed on a wafer wherein each semiconductor device comprises a plurality of input/output terminals, the probe card assembly comprising:

a rigid substrate;

an electrical interface;

a plurality of probes disposed on the substrate and arranged to contact ones of the input/output terminals;

a plurality of switches interconnecting ones of the probes to electrical interconnections, wherein the electrical interconnections comprise an electrical bus; and

a means for controlling the switches to enable each of the probes corresponding to the input/output terminals of a failed one of the plurality of semiconductor devices to be disconnected from the electrical interconnections,

wherein the electrical interconnections are electrically connected to the electrical interface and comprise;

a first electrical bus interconnected to first ones of the input/output terminals of the semiconductor devices through a plurality of first switches of the plurality of switches; and

a second electrical bus interconnected to second ones of the input/output terminals of the semiconductor devices to through a plurality of second switches of the plurality of switches,

wherein ones of the second switches corresponding to the failed one of the plurality of semiconductor devices are opened to disconnect the failed one of the plurality of semiconductor devices from the second electrical bus when a failure of the failed one of the plurality of semiconductor devices is detected on the first electrical bus.

10. The probe card assembly of claim 9, further comprising means for accepting a map of known bad ones of the plurality of semiconductor devices on the wafer via the electrical interface.

11. The probe card assembly of claim 9, further comprising means for performing a continuity check.

12. The probe card assembly of claim 9, further comprising an overcurrent detector for determining a failed one of the plurality of semiconductor devices.

13. The probe card assembly of claim 9, further comprising a memory configured to store fault information identifying the failed one of the plurality of semiconductor devices.

14. The probe card assembly of claim 9, further comprising a communication interface configured to communicate fault information between the probe card assembly and a tester, the fault information comprising identification of the failed one of the plurality of semiconductor devices.

15. The probe card assembly of claim 9, wherein the electrical interconnections comprise a power bus and a signal bus.

16. The probe card assembly of claim 9, further comprising a power converter configured to perform a power conversion between an input power provided to the probe card assembly and power supplied to the semiconductor devices.

17. The probe card assembly of claim 9, wherein the switches are selected from the group consisting of:

an electromechanical relay, a transistor, a thyristor, and a photo coupled field effect transistor.

18. A probe card assembly for testing semiconductor dies of a semiconductor wafer having a plurality of terminals disposed thereon, the probe card assembly comprising:

a rigid substrate;

an electrical interface to a tester for controlling testing of the semiconductor dies;

a plurality of probes disposed on the substrate and arranged to contact corresponding ones of the plurality of terminals of the semiconductor dies;

a continuity tester means for testing an electrical path between the electrical interface to the tester and one of the probes for a short circuit fault and an open circuit fault in the electrical path; and

a plurality of switches interconnecting the plurality of probes to the continuity tester means, the switches enabling the continuity tester means to be electrically connected to a selected one of the plurality of probes;

wherein the continuity tester means is for testing the electrical path between the electrical interface to the tester and one of the probes for the short circuit fault and the open circuit fault while the probes are disconnected from the terminals of the semiconductor dies.

19. The probe card assembly of claim 18, further comprising means for performing a self test of the probe card assembly using the continuity tester means.

20. The probe card assembly of claim 18, wherein the switches are selected from the group consisting of:

an electromechanical relay, a transistor, a thyristor, and a photo coupled field effect transistor.