Apparatus and method for linearizing field effect transistors in the OHMIC region

• US 8,400,205 B2
• Filed: 04/08/2011
• Issued: 03/19/2013
• Est. Priority Date: 04/08/2011
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Foroudi, Omid
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US13/082,803
• Publication Number:
  US 20120256674A1
• Time in Patent Office: 711 Days
• Field of Search: 327/427, 327/365, 327/376, 327/377, 327/307, 327/308
• US Class Current: 327/308
• CPC Class Codes: H03H 11/245 using field-effect transistor

Abstract

Apparatus and methods are disclosed related to using one or more field effect transistors as a resistor. One such apparatus includes a field effect transistor with a first series circuit in parallel with the gate and the source of the field effect transistor and a second series circuit in parallel with the gate and the drain of the field effect transistor. Each series circuit can include a capacitor and a switch in series with the capacitor. The switch can be configured to be on when the field effect transistor is on, and to be off when the field effect transistor is off. This can improve the linearity of the field effect transistor as a resistor. In some implementations, the apparatus can further include an isolation resistor having a first end and a second end, the first end electrically coupled to the gate of the field effect transistor.

Claims

1. An apparatus comprising:

a field effect transistor having a gate, a source, and a drain;

a first series circuit in parallel with the gate and the source of the field effect transistor, the first series circuit comprising;

a first capacitor; and

a first switch in series with the first capacitor, wherein the first switch is configured to be on when the field effect transistor is on, and to be off when the field effect transistor is off; and

a second series circuit in parallel with the gate and the drain of the field effect transistor, the second series circuit comprising;

a second capacitor; and

a second switch in series with the second capacitor, wherein the second switch is configured to be on when the field effect transistor is on, and to be off when the field effect transistor is off.

2. The apparatus of claim 1, further comprising a resistor having a first end and a second end, the first end electrically coupled to the gate of the field effect transistor.

3. The apparatus of claim 1, wherein the field effect transistor is an NMOS device.

4. The apparatus of claim 1, wherein a capacitance of the first capacitor is approximately equal to a capacitance of the second capacitor.

5. The apparatus of claim 1, wherein the first series circuit and the second series circuit are configured to provide an averaging voltage to the gate of the field effect transistor when the first switch and the second switch are on, the averaging voltage including an average of a voltage at the drain of the field effect transistor and a voltage at the source to the gate of the field effect transistor.

6. The apparatus of claim 1, wherein the first switch is electrically coupled in series between the first capacitor and the source of the field effect transistor.

7. The apparatus of claim 1, wherein the first switch comprises a first field effect transistor, and the second switch comprises a second field effect transistor.

8. The apparatus of claim 7, wherein the field effect transistor has a width that is at least about twice as large as a width of the first field effect transistor.

9. The apparatus of claim 7, wherein the gate of the field effect transistor is electrically coupled to a gate of the first field effect transistor and a gate of the second field effect transistor.

10. The apparatus of claim 1, wherein the field effect transistor is biased to operate in the linear mode of operation when on.

11. An apparatus comprising:

a variable resistance circuit configured to generate an output based on an input and a plurality of control signals, the variable resistance circuit comprising a plurality of linear resistance circuits, wherein each linear resistance circuit comprises;

a field effect transistor having a gate, a source, and a drain, the gate controlled by a control signal of the plurality of control signals, the drain configured to receive the input, and the source configured to drive the output when the field effect transistor is on;

a first series circuit in parallel with the gate and the source of the field effect transistor, the first series circuit comprising;

a first capacitor; and

a first switch in series with the first capacitor, wherein the first switch is configured to be on when the field effect transistor is on, and to be off when the field effect transistor is off; and

a second series circuit in parallel with the gate and the drain of the field effect transistor, the second series circuit comprising;

a second capacitor; and

a second switch in series with the second capacitor, wherein the second switch is configured to be on when the field effect transistor is on, and to be off when the field effect transistor is off;

wherein each of the plurality of linear resistance circuits is configured to switch the field effect transistor based on one of the plurality of control signals.

12. The apparatus of claim 11, wherein the variable resistance circuit is embodied in a programmable filter.

13. The apparatus of claim 11, further comprising an analog to digital converter wherein the output of the variable resistance circuit is provided as an input to the analog to digital converter.

14. The apparatus of claim 11, wherein the field effect transistor of a first linear resistance circuit of the plurality of linear resistance circuits has a width that is a multiple of a width of the field effect of a second linear resistance circuit of the plurality of linear resistance circuits, and wherein the multiple is a positive integer power of two.

15. The apparatus of claim 11, wherein the variable resistance circuit is configured to adjust the bandwidth of the output by selectively activating the field effect transistors in the plurality of linear resistance circuits based at least partly on states associated with the plurality of control signals.

16. The apparatus of claim 11, wherein the output has a bandwidth ranging from about 5 MHz to 40 MHz.

17. A method of using a field effect transistor, the method comprising:

controlling activation of the field effect transistor based at least partly on one or more control signals, the field effect transistor having a gate, a source, and a drain;

filtering an input signal with the field effect transistor when the field effect transistor operates in the ohmic region; and

controlling filtering such that;

a first switch electrically couples a first capacitor in parallel with the gate and the drain of the field effect transistor when the field effect transistor is on, and the first switch does not electrically couple the first capacitor in parallel with the gate and the drain of the field effect transistor when the field effect transistor is off; and

a second switch electrically couples a second capacitor in parallel with the gate and the source of the field effect transistor when the field effect transistor is on, and the second switch does not electrically couple the second capacitor in parallel with the gate and the source of the field effect transistor when the field effect transistor is off.

18. The method of claim 17, further comprising isolating a parasitic capacitance between the gate and the drain and a parasitic capacitance between the gate and the source from alternating current ground via an isolation resistor.

19. The method of claim 17, wherein controlling filtering includes providing an average of a voltage at the drain of the field effect transistor and a voltage at the source to the gate of the field effect transistor when the first switch and the second switch are on.

20. The method of claim 17, wherein the first switch includes a first field effect transistor having a gate, a source, and a drain, and wherein the gate of the field effect transistor is electrically coupled to the gate of the first field effect transistor.