Via-less thin film resistor with a dielectric cap

• US 8,400,257 B2
• Filed: 08/24/2010
• Issued: 03/19/2013
• Est. Priority Date: 08/24/2010
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV), Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Inventors: Lim, Ting Fang, Niu, Chengyu, Le Neel, Olivier, Leung, Calvin
• Primary Examiner(s): LEE, KYUNG S
• Application Number:
  US12/862,599
• Publication Number:
  US 20120049997A1
• Time in Patent Office: 938 Days
• Field of Search: 438/384, 438/648, 438/685, 338/308
• US Class Current: 338/308
• CPC Class Codes: H01C 1/148 the terminals embracing or surrounding the resistive element H01C1/142 takes precedence
• CPC Class Codes: H01C 7/006 Thin film resistors
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 2221/1078 Multiple stacked thin films not being formed in openings in dielectrics
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/24 with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 29/49099 Coating resistive material on a base

Abstract

The present disclosure is directed to a thin film resistor structure that includes a resistive element electrically connecting first conductor layers of adjacent interconnect structures. The resistive element is covered by a dielectric cap layer that acts as a stabilizer and heat sink for the resistive element. Each interconnect includes a second conductor layer over the first conductive layer. The thin film resistor includes a chromium silicon resistive element covered by a silicon nitride cap layer.

Claims

1. A method, comprising:

forming a first interconnect spaced from a second interconnect over a substrate, the forming comprising;

forming a first conductor over the substrate;

forming a second conductor over the first conductor; and

defining the first and second interconnects by removing portions of the first and second conductors and forming first and second sidewalls of the first and second interconnects, respectively, the first and second sidewalls being transverse to the substrate;

forming a resistive layer over the first and second interconnects;

forming a dielectric cap layer over the resistive layer; and

forming a capped thin film resistor electrically connecting a first remaining portion of the first conductor in the first interconnect to a second remaining portion of the first conductor in the second interconnect, the forming including removing portions of the resistive layer and the dielectric cap layer.

2. The method of claim 1 wherein the capped thin film resistor includes a first portion over the substrate between the first and second interconnects and second portions transverse to the first portion, the second portions abutting the first and second sidewalls of the first and second interconnects, respectively.

3. The method of claim 1 wherein a top surface of the capped thin film resistor is below a top surface of the substrate.

4. The method of claim 1 wherein forming the resistive layer includes depositing a chromium silicon film by sputtering.

5. The method of claim 1 wherein the dielectric cap is silicon nitride.

6. The method of claim 1 wherein forming the resistive layer includes forming a first resistive layer over the substrate and forming a second resistor layer over the first resistor layer.

7. The method of claim 6 wherein the first resistive layer has a first temperature coefficient of resistance and the second resistive layer has a second temperature coefficient of resistance having an opposite sign from first temperature coefficient of resistance.

19. The method of claim 1 comprising:

forming a dielectric layer over the first and second interconnects and the resistive layer;

forming conductive vias through the dielectric layer to the first and second interconnects; and

forming a third and a fourth interconnects coupled to the first and second interconnects, respectively, through the vias.

20. The method of claim 1, wherein forming a capped thin film resistor comprises:

forming a photoresist layer over portions of a top surface of the first and second interconnects and over a portion of the substrate between the first and second interconnects; and

etching the resistive layer to expose the substrate not covered by the photoresist layer.

8. A method, comprising:

forming a first conductive layer over a substrate;

forming a second conductive layer over the first conductive layer;

removing portions of the first and second conductive layers to form a first interconnect structure and a second interconnect structure spaced from the first interconnect structure over the substrate, each interconnect structure including a respective portion of the first conductive layer and a respective portion of the second conductive layer;

forming a resistive layer over the first and second interconnect structures and the substrate; and

defining a thin film resistor electrically connecting sidewalls of the first conductive layers of the first and second interconnect structures to each other, the defining including removing portions of the resistive layer.

9. The method of claim 8, further comprising:

forming a protective coating over the second conductive layer prior to forming the first and second interconnect structures.

10. The method of claim 8 wherein defining the thin film resistor further comprises:

forming a photoresist layer over portions of a top surface of the first and second interconnect structures and over a portion of the substrate between the first and second interconnect structures; and

etching the resistive layer to expose the substrate not covered by the photoresist layer.

11. The method of claim 8, further comprising:

forming a dielectric layer over the first and second interconnect structures and the thin film resistor;

forming conductive vias through the dielectric layer to the first and second interconnect structures; and

forming a third and a fourth interconnect structure coupled to the first and second interconnect structures, respectively, through the vias.

12. The method of claim 8, further comprising forming a dielectric cap over the thin film resistor.

13. The method of claim 8 wherein forming the resistive layer includes forming a first resistive layer over the substrate and forming a second resistor layer over the first resistor layer.

14. A method, comprising:

forming first and second interconnect structures over a substrate of an integrated circuit die, each interconnect structure having a first conductor layer;

forming a resistive layer over the substrate electrically connecting sidewalls of the first conductor layers of the first and second interconnect structures together;

defining a thin film resistor between first and second interconnect structures by removing portions of the resistive layer;

forming a dielectric layer over the first and second interconnect structures and the thin film resistor;

forming conductive vias through the dielectric layer to the first and second interconnect structures; and

forming a third and a fourth interconnect structure coupled to the first and second interconnect structures, respectively, through the vias.

15. The method of claim 14, further comprising forming a second conductor layer over the first conductor layer of the first and second interconnect structures.

16. The method of claim 14 wherein the resistive layer is less than 200 angstroms in thickness.

17. The method of claim 14 comprising forming a transistor below the substrate prior to forming the resistive layer.

18. The method of claim 17 wherein the first and second interconnect structures each include a first metal on a second metal, the resistive layer being in contact with the first metal and the second metal of the first and the second interconnect structures.

21. A method, comprising:

forming first and second interconnect structures over a substrate of an integrated circuit die, each interconnect structure having a first conductor layer;

forming a resistive layer over the substrate electrically connecting sidewalls of the first conductor layers of the first and second interconnect structures together;

defining a thin film resistor between first and second interconnect structures by removing portions of the resistive layer, the removing including;

forming a photoresist layer over portions of a top surface of the first and second interconnect structures and over a portion of the substrate between the first and second interconnect structures; and

etching the resistive layer to expose the substrate not covered by the photoresist layer.

22. The method of claim 21, further comprising forming a second conductor layer over the first conductor layer of the first and second interconnect structures.