Power layer generation of inverter gate drive signals
First Claim
1. A system for controlling operation of power inverter switches, comprising:
- control circuitry configured to generate gate timing-related signals for timing of state changes of the switches;
a data conductor coupled to the control circuitry for conveying the gate timing-related signals from the control circuitry;
power layer circuitry coupled to the data conductor and configured to receive the gate timing-related signals and to recomputed the timing for the state changes based upon the received gate timing-related signals; and
a plurality of solid state switches coupled to the power layer circuitry and configured to change state to convert input power to controlled output power based upon the recomputed timing;
wherein the control circuitry is configured to periodically transmit synchronization signals to the power layer circuitry and the power layer circuitry is configured to adjust a power layer clock between the synchronization signals to compensate for variability in an operating frequency of an oscillator upon which the power layer clock is based.
1 Assignment
0 Petitions
Accused Products
Abstract
Techniques include systems and methods of synchronizing multiple parallel inverters in a power converter system. In one embodiment, control circuitry is connected to a power layer interface circuitry at each of the parallel inverters, via an optical fiber interface. The system is synchronized by transmitting a synchronizing pulse to each of the inverters. Depending on the operational mode of the system, different data exchanges may occur in response to the pulse. In an off mode, power up and power down data may be exchanged between the control circuitry and the inverters. In an initiating mode, identification data may be transmitted from the inverters to the control circuitry. In an active mode, control data may be sent from the control circuitry to the inverters. In some embodiments, the inverters also transmit feedback data and/or acknowledgement signals to the control circuitry. Power layer circuitry of the inverter adjusts a local clock based upon sampled data from the control circuitry to maintain synchronicity of the inverters between synchronization pulses.
-
Citations
6 Claims
-
1. A system for controlling operation of power inverter switches, comprising:
-
control circuitry configured to generate gate timing-related signals for timing of state changes of the switches; a data conductor coupled to the control circuitry for conveying the gate timing-related signals from the control circuitry; power layer circuitry coupled to the data conductor and configured to receive the gate timing-related signals and to recomputed the timing for the state changes based upon the received gate timing-related signals; and a plurality of solid state switches coupled to the power layer circuitry and configured to change state to convert input power to controlled output power based upon the recomputed timing; wherein the control circuitry is configured to periodically transmit synchronization signals to the power layer circuitry and the power layer circuitry is configured to adjust a power layer clock between the synchronization signals to compensate for variability in an operating frequency of an oscillator upon which the power layer clock is based. - View Dependent Claims (2, 3, 4, 5, 6)
-
Specification
-
- Resources
-
Current AssigneeRockwell Automation Technologies Incorporated (Rockwell Automation, Inc.)
-
Original AssigneeRockwell Automation Technologies Incorporated (Rockwell Automation, Inc.)
-
InventorsCampbell, Alan J., Radosevich, Richard H.
-
Primary Examiner(s)NGUYEN, MATTHEW VAN
-
Application NumberUS12/838,255Publication NumberTime in Patent Office977 DaysField of Search363/34, 363/37, 363/65, 363/71, 323349-351, 327/141, 327144-146US Class Current363/34CPC Class CodesH02M 7/537 using semiconductor devices...H03K 5/135 by the use of time referenc...
