Device to program adjacent storage cells of different NROM cells
First Claim
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1. A nitride read only memory (NROM) non-volatile memory device comprising:
- an array of charge trapping type memory cells connected to word lines and local bit lines;
said array comprising global bit lines, select transistors connecting said global bit lines to said local bit lines and select lines to activate said select transistors;
circuitry for programming at generally a same time two adjacent storage areas of two different NROM cells which share a local bit line and for reading at generally a same time said two adjacent storage areas;
wherein programming comprises concurrently applying the same programming pulse to the two adjacent storage areas, and wherein said select transistors are organized such that any set of three consecutive local bit lines are connected to three different global bit lines.
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Abstract
A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local bit lines of two neighboring memory cells to a receiving unit, such as a ground supply or two sense amplifiers. Also included is an array performing the method.
300 Citations
12 Claims
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1. A nitride read only memory (NROM) non-volatile memory device comprising:
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an array of charge trapping type memory cells connected to word lines and local bit lines;
said array comprising global bit lines, select transistors connecting said global bit lines to said local bit lines and select lines to activate said select transistors;circuitry for programming at generally a same time two adjacent storage areas of two different NROM cells which share a local bit line and for reading at generally a same time said two adjacent storage areas; wherein programming comprises concurrently applying the same programming pulse to the two adjacent storage areas, and wherein said select transistors are organized such that any set of three consecutive local bit lines are connected to three different global bit lines. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A nitride read only memory (NROM) non-volatile memory device comprising:
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an array having charge trapping type memory cells connected to word lines and local bit lines;
said array comprising global bit lines, select transistors connecting said global bit lines to said local bit lines and select lines to activate said select transistors; andcircuitry for activating, at generally the same time, three global bit lines during programming of two adjacent neighboring storage areas of two different NROM cells which share a local bit line, such that the neighboring storage areas are concurrently programmed to a non-erased state, and for activating said three global bit lines for concurrently reading said two adjacent neighboring storage areas; wherein programming comprises concurrently applying the same programming pulse to the two adjacent storage areas, and wherein said select transistors are organized such that any set of three consecutive local bit lines are connected to three different global bit lines. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification