Semiconductor memory module

• US 8,400,869 B2
• Filed: 02/08/2011
• Issued: 03/19/2013
• Est. Priority Date: 02/26/2010
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Musha, Tatsunori
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US13/023,068
• Publication Number:
  US 20110211414A1
• Time in Patent Office: 770 Days
• Field of Search: 365/233.13, 365/233.1, 365/233.12, 365/233.18, 365/239, 365/230.06, 365/189.17, 365/189.12
• US Class Current: 365/233.13
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A semiconductor device includes a plurality of semiconductor memories, a clock signal synchronization circuit, and a first circuit. The clock signal synchronization circuit is electrically coupled to the plurality of semiconductor memories. The first circuit is electrically coupled to the plurality of semiconductor memories. The first circuit changes a bit width of data. The data is transferred between the first circuit and the plurality of semiconductor memories.

Claims

1. A semiconductor device:

a plurality of semiconductor memories;

a clock signal synchronization circuit electrically coupled to the plurality of semiconductor memories; and

a first circuit electrically coupled to the plurality of semiconductor memories, the first circuit changing a bit width of data, the data being transferred between the first circuit and the plurality of semiconductor memories,

wherein the clock signal synchronization circuit is electrically coupled to the first circuit,

wherein the clock signal synchronization circuit generates a first clock synchronized with an external clock, and

wherein the first circuit receives the first clock.

2. The semiconductor device according to claim 1, further comprising:

a dividing circuit receiving the first clock from the clock signal synchronization circuit, the dividing circuit generating a second clock from the first clock, the second clock being in synchronism with the first clock, and the second clock having a different frequency from that of the first clock.

3. The semiconductor device according to claim 2, wherein the first circuit receives the second clock from the dividing circuit,

wherein the first circuit receives the first clock from the clock signal synchronization circuit, and

wherein the first circuit operates based on the first and second clocks.

4. The semiconductor device according to claim 3, wherein the first circuit increases the bit width of the data when the semiconductor device is placed in write operation.

5. The semiconductor device according to claim 3, wherein the first circuit decreases the bit width of the data when the semiconductor device is placed in read operation.

6. The semiconductor device according to claim 2, wherein the dividing circuit supplies the second clock to the plurality of semiconductor memories.

7. The semiconductor device according to claim 1, wherein the first circuit comprises a parallel-serial conversion circuit.

8. The semiconductor device according to claim 1, wherein the clock signal synchronization circuit and the first circuit are integrated on an interface chip.

9. The semiconductor device according to claim 1, wherein the plurality of semiconductor memories perform a first burst operation with a first burst length, the first circuit performs a second burst operation with a second burst length, the first burst length is shorter than the second burst length.

10. The semiconductor device according to claim 1, further comprising:

a plurality of command decoders, each of the plurality of command decoders corresponding to a corresponding one of a plurality of memory banks.

11. The semiconductor device according to claim 10, wherein each of the plurality of command decoders decodes a command to the corresponding one of the plurality of banks, the corresponding one is placed in an active mode or a standby mode according to the command.

12. The semiconductor device according to claim 1, further comprising:

a bus width switch switching a bit number of data to be input into the first circuit.

13. A semiconductor device comprising:

a plurality of semiconductor memories; and

an interface chip electrically coupled in parallel to the plurality of semiconductor memories,

wherein the interface chip comprises;

a clock signal synchronization circuit generating a first clock synchronized with an external clock;

a dividing circuit receiving the first clock from the clock signal synchronization circuit, the dividing circuit generating a second clock from the first clock, the second clock being in synchronism with the first clock, and the second clock having a different frequency from that of the first clock, the dividing circuit supplying the second clock to the plurality of semiconductor memories; and

a parallel-serial conversion circuit electrically coupled to the plurality of semiconductor memories, the parallel-serial conversion circuit increasing a first bit width of data to be transferred to the plurality of semiconductor memories when the semiconductor device is placed in write operation, the parallel-serial conversion circuit decreasing a second bit width of data to have been transferred from the plurality of semiconductor memories when the semiconductor device is placed in read operation.

14. The semiconductor device according to claim 13, wherein the interface chip further comprises:

a command decoder decoding a command to at least one of the plurality of semiconductor memories, the at least one of the plurality of semiconductor memories performing an operation according to the command.

15. A semiconductor device comprising:

a plurality of banks, each of the plurality of banks comprising a plurality of semiconductor memories;

an interface chip electrically coupled in parallel to the plurality of semiconductor memories; and

a boosted voltage generation circuit supplying a boosted voltage to the plurality of the semiconductor memories,

wherein the interface chip comprises;

a clock signal synchronization circuit generating a first clock synchronized with an external clock;

a dividing circuit receiving the first clock from the clock signal synchronization circuit, the dividing circuit generating a second clock from the first clock, the second clock being in synchronism with the first clock, and the second clock having a different frequency from that of the first clock, the dividing circuit supplying the second clock to the plurality of semiconductor memories;

a plurality of command decoders, each of the plurality of command decoders corresponding to a corresponding one of the plurality of banks;

a parallel-serial conversion circuit electrically coupled to the plurality of semiconductor memories, the parallel-serial conversion circuit increasing a first bit width of data to be transferred to the plurality of semiconductor memories when the semiconductor device is placed in write operation, the parallel-serial conversion circuit decreasing a second bit width of data to have been transferred from the plurality of semiconductor memories when the semiconductor device is placed in read operation;

an error correcting code circuit adding error correction code bit data to data to be written in the plurality of the semiconductor memories; and

a bus width switch switching a bit number of data to be input into the parallel-serial conversion circuit.

16. A semiconductor device comprising:

a plurality of semiconductor memory chips; and

an interface chip electrically coupled to each of the semiconductor memory chips, the interface chip comprising;

a clock signal synchronization circuit receiving an external clock and generating a first internal clock that is synchronized with the external clock;

a first set of data terminals;

a second set of data terminals electrically coupled to the semiconductor memory chips; and

a parallel-serial conversion circuit electrically coupled between the first and second sets of data terminals, the parallel-serial conversion circuit being electrically coupled to the clock signal synchronization circuit to receive the first internal clock and performing, in response to the first internal clock, a serial-to-parallel conversion operation on data supplied in series to the first set of data terminals and a parallel-to-serial conversion operation on data supplied in parallel to the second set of data terminals from the semiconductor memory chips.

17. The device as claimed in claim 16, wherein the clock signal synchronization circuit comprises one of a DLL circuit and a PLL circuit.

18. The device as claimed in claim 16, wherein the data supplied in series to the first set of data terminals are converted into parallel data by the serial-to-parallel conversion operation of the parallel-serial circuit, the parallel data being transferred to the semiconductor memory chips through the second set of data terminals, and the data supplied in parallel to the second set of data terminals from the semiconductor memory chips are converted into serial data by the parallel-to-serial conversion operation of the parallel-serial circuit, the serial data being transferred to the first set of data terminals.

19. The device as claimed in claim 18, wherein the second set of data terminals is greater in number than the first set of data terminals so that the data supplied in series to the first set of data terminals are smaller in number of bits than the data supplied in parallel to the second set of data terminals from the semiconductor memory chips.

20. The device as claimed in claim 17,

wherein the interface chip further comprises a clock circuit generating a second internal clock that is lower in frequency than the internal clock,

wherein the data supplied in series to the first set of data terminals are converted into parallel data by the serial-to-parallel conversion operation of the parallel-serial circuit responsive to the first internal clock, the parallel data being transferred to the semiconductor memory chips through the second set of data terminals in response to the second internal clock, and

wherein the data from the semiconductor memory chips are supplied in parallel to the second set of data terminals in response to the second internal clock and are converted into serial data by the parallel-to-serial conversion operation of the parallel-serial circuit responsive to the first internal clock, the serial data being transferred to the first set of data terminals.