Inverse quantization circuit, inverse quantization method and image reproducing apparatus

• US 8,401,073 B2
• Filed: 02/26/2008
• Issued: 03/19/2013
• Est. Priority Date: 03/28/2007
• Status: Expired due to Fees

• Current Assignee: Sovereign Peak Ventures, LLC (Dominion Harbor Enterprises, LLC)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Yoshimatsu, Naoki
• Primary Examiner(s): Gergiso, Techane
• Application Number:
  US12/438,927
• Publication Number:
  US 20100014582A1
• Time in Patent Office: 1,848 Days
• Field of Search: 375/240.03, 375/240.25
• US Class Current: 375/240.03
• CPC Class Codes: H04N 19/126 Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
• CPC Class Codes: H04N 19/157 Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter
• CPC Class Codes: H04N 19/18 the unit being a set of transform coefficients
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/60 using transform coding
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

Provided are a versatile inverse quantization circuit which performs inverse quantization operable for various encoding systems by a single circuit, an inverse quantization method, and an image reproducing apparatus. A first multiplier generation unit (10) generates a first multiplier M1, a second multiplier generation unit (20) generates a second multiplier M2, a shift quantity generation unit (180) generates shift quantity data SF indicating a bit shift quantity, a multiplication unit (140) multiplies quantized coefficient data CD by the first multiplier M1 and the second multiplier M2, a shift unit (170) carries out bit shift operation in accordance with the shift quantity data SF, at least one of the multiplication unit (140) and the shift unit (170) determines whether or not to perform operation depending on the encoding system, and at least one of the first multiplier generation unit (10), the second multiplier generation unit (20) and the shift quantity generation unit (180) determines a value to be generated or a way of generating the value depending on the encoding system.

Claims

1. An inverse quantization circuit that adaptively handles performance of inverse quantization for plural encoding systems by selectively performing operations depending on a present encoding system from among the plural encoding systems, said inverse quantization circuit comprising:

a first multiplier generation unit that generates a first multiplier, wherein the first multiplier generation unit determines the first multiplier or a way of generating the first multiplier depending on the present encoding system;

a second multiplier generation unit that generates a second multiplier, wherein the second multiplier generation unit determines the second multiplier or a way of generating the second multiplier depending on the present encoding system;

a shift quantity generation unit that generates shift quantity data indicating a bit shift quantity;

a multiplication unit that determines whether or not to perform a multiplication operation depending on the present encoding system, and when determined affirmatively, performs the multiplication operation which comprises multiplying quantized coefficient data by the first multiplier generated by the first multiplier generation unit and the second multiplier generated by the second multiplier generation unit, wherein the quantized coefficient data is a result of quantization of a coefficient value for each frequency obtained by transforming image data based on an encoding system;

a shift unit that determines whether or not to perform a bit shift operation depending on the present encoding system, and when determined affirmatively, performs the bit shift operation to the data outputted from the multiplication unit according to the shift quantity data generated by the shift quantity generation unit;

an addend generation unit that generates an addend, wherein the addend generation unit determines the addend or a way of generating the addend depending on the present encoding system; and

an addition unit that determines whether or not to perform an addition operation depending on the present encoding system, and when determined affirmatively, performs the addition operation which comprises adding the addend generated by the addend generation unit to the data outputted from the multiplication unit,

wherein the shift unit performs the bit shift operation to the data outputted from the addition unit or to the data outputted from the multiplication unit depending on the present encoding system, according to the shift quantity data generated by the shift quantity generation unit.

2. The inverse quantization circuit according to claim 1, wherein the first multiplier generation unit generates the first multiplier including a quantization scale value indicating a quantization width, and

the second multiplier generation unit generates the second multiplier including a quantization matrix value indicating a quantization width for each frequency.

3. The inverse quantization circuit according to claim 1, wherein the multiplication unit selects one value of a value resulting from multiplication of the quantized coefficient data by the first multiplier, a value resulting from multiplication of the quantized coefficient data by the second multiplier and a value resulting from multiplication of the quantized coefficient data by the first multiplier and the second multiplier and supplies the selected value to the addition unit as output data.

4. The inverse quantization circuit according to claim 1, wherein the addition unit selects one value of a value of data supplied from the multiplication unit and a value resulting from addition of the addend generated by the addend generation unit to the data supplied from the multiplication unit and supplies the selected value to the shift unit as output data.

5. The inverse quantization circuit according to claim 1, wherein the shift unit selects one value of a value of data supplied from the addition unit and a value obtained through the bit shift operation and outputs the selected value as output data.

6. The inverse quantization circuit according to claim 1, further comprising a rounding unit that performs rounding processing by adding a value in accordance with the shift quantity data generated by the shift quantity generation unit to the output data from the addition unit, selectively switches between the processed data subjected to the rounding processing and non-processed data not subjected to the rounding processing and outputs the data to the shift unit.

19. An image reproducing apparatus comprising:

a quantized coefficient data acquiring unit that acquires quantized coefficient data;

an inverse quantization circuit according to claim 1 that reconstructs a coefficient value by inverse-quantizing the quantized coefficient data acquired by the quantized coefficient data acquiring unit;

a transforming unit that transforms the coefficient value reconstructed by the inverse quantization circuit to image data; and

an output unit that outputs the image data transformed by the transforming unit.

7. An inverse quantization circuit that adaptively handles performance of inverse quantization for plural encoding systems by selectively performing operations depending on a present encoding system from among the plural encoding systems, said inverse quantization circuit comprising:

a first multiplier generation unit that generates a first multiplier, wherein the first multiplier generation unit determines the first multiplier or a way of generating the first multiplier depending on the present encoding system;

a second multiplier generation unit that generates a second multiplier, wherein the second multiplier generation unit determines the second multiplier or a way of generating the second multiplier depending on the present encoding system;

a shift quantity generation unit that generates shift quantity data indicating a bit shift quantity;

a multiplication unit that determines whether or not to perform a multiplication operation depending on the present encoding system, and when determined affirmatively, performs the multiplication operation which comprises multiplying quantized coefficient data by the first multiplier generated by the first multiplier generation unit and the second multiplier generated by the second multiplier generation unit, wherein the quantized coefficient data is a result of quantization of a coefficient value for each frequency obtained by transforming image data based on an encoding system; and

a shift unit that determines whether or not to perform a bit shift operation depending on the present encoding system, and when determined affirmatively, performs the bit shift operation to the data outputted from the multiplication unit according to the shift quantity data generated by the shift quantity generation unit,

wherein the first multiplier generation unit generates the first multiplier including a quantization scale value indicating a quantization width,

wherein the second multiplier generation unit generates the second multiplier including a quantization matrix value indicating a quantization width for each frequency,

wherein the first multiplier generation unit comprises;

a scale value generation section that generates the quantization scale value; and

a scale processing section that applies an operation to the quantization scale value and outputs one of the quantization scale value and the value obtained through the operation as the first multiplier, and

wherein the second multiplier generation unit comprises a matrix value generation section that generates the quantization matrix value for each frequency and outputs the generated quantization matrix value as the second multiplier.

8. The inverse quantization circuit according to claim 7, wherein the scale processing section outputs one of the quantization scale value, the value obtained by performing the operation to the quantization scale value and a predetermined constant value as the first multiplier, and

the matrix value generation section outputs one of the quantization matrix value for each frequency and a predetermined constant value as the second multiplier.

9. The inverse quantization circuit according to claim 7, wherein the addend generation unit comprises:

a multiplier that multiplies the quantization scale value generated by the scale value generation section and the quantization matrix value generated by the matrix value generation section; and

a selection unit that selects one value of the quantization scale value, the quantization matrix value and the value obtained by multiplying the quantization scale value and the quantization matrix value and supplies the selected value to the addition unit as the addend.

10. The inverse quantization circuit according to claim 9, wherein the selection unit selects one value of the quantization scale value, the quantization matrix value, the value obtained by multiplying the quantization scale value and the quantization matrix value and a predetermined constant value and supplies the selected value to the addition unit as the addend.

11. The inverse quantization circuit according to claim 7, wherein the scale value generation section comprises:

one or a plurality of types of first scale conversion unit that converts supplied data to a quantization scale value;

a second scale conversion unit that further converts the quantization scale value converted by the first scale conversion unit; and

a selection unit that selects one of the quantization scale value converted by the first scale conversion unit and the quantization scale value converted by the second scale conversion unit and outputs the selected quantization scale value to the scale processing section.

12. The inverse quantization circuit according to claim 11, wherein the shift quantity generation unit comprises a shift quantity conversion unit that converts the quantization scale value outputted from the scale conversion unit of the scale value generation section to the shift quantity data.

13. The inverse quantization circuit according to claim 12, wherein the shift quantity generation unit comprises a selection unit that selects one of the shift quantity data converted by the shift quantity conversion unit and a predetermined constant value as the shift quantity data and supplies the selected shift quantity data to the shift unit.

14. The inverse quantization circuit according to claim 12, wherein the shift quantity generation unit further comprises an adder that supplies a value resulting from addition of a shift addend to the shift quantity data converted by the shift quantity conversion unit to the shift unit as shift quantity data.

15. The inverse quantization circuit according to claim 7, wherein the scale processing section comprises:

an operation unit that applies an operation to the quantization scale value generated by the scale value generation section; and

a selection unit that selects one of the quantization scale value generated by the scale value generation section, the quantization scale value subjected to the operation by the operation unit and a predetermined constant value and outputs the selected value as the first multiplier.

16. An inverse quantization circuit that adaptively handles performance of inverse quantization for plural encoding systems by selectively performing operations depending on a present encoding system from among the plural encoding systems, said inverse quantization circuit comprising:

a first multiplier generation unit that generates a first multiplier, wherein the first multiplier generation unit determines the first multiplier or a way of generating the first multiplier depending on the present encoding system;

a second multiplier generation unit that generates a second multiplier, wherein the second multiplier generation unit determines the second multiplier or a way of generating the second multiplier depending on the present encoding system;

a shift quantity generation unit that generates shift quantity data indicating a bit shift quantity;

a multiplication unit that determines whether or not to perform a multiplication operation depending on the present encoding system, and when determined affirmatively, performs the multiplication operation which comprises multiplying quantized coefficient data by the first multiplier generated by the first multiplier generation unit and the second multiplier generated by the second multiplier generation unit, wherein the quantized coefficient data is a result of quantization of a coefficient value for each frequency obtained by transforming image data based on an encoding system;

a shift unit that determines whether or not to perform a bit shift operation depending on the present encoding system, and when determined affirmatively, performs the bit shift operation to the data outputted from the multiplication unit according to the shift quantity data generated by the shift quantity generation unit; and

a post-processing unit that includes an operation function that performs discrete cosine transform mismatch control processing on the data outputted from the shift unit and an operation function that performs saturation processing capable of setting a range of clipping the data outputted from the shift unit, selectively switches between processed data and non-processed data in the discrete cosine transform mismatch control processing and the saturation processing respectively, and outputs the data.

17. An inverse quantization circuit that adaptively handles performance of inverse quantization for plural encoding systems by selectively performing operations depending on a present encoding system from among the plural encoding systems, said inverse quantization circuit comprising:

a first multiplier generation unit that generates a first multiplier, wherein the first multiplier generation unit determines the first multiplier or a way of generating the first multiplier depending on the present encoding system;

a second multiplier generation unit that generates a second multiplier, wherein the second multiplier generation unit determines the second multiplier or a way of generating the second multiplier depending on the present encoding system;

a shift quantity generation unit that generates shift quantity data indicating a bit shift quantity;

a multiplication unit that determines whether or not to perform a multiplication operation depending on the present encoding system, and when determined affirmatively, performs the multiplication operation which comprises multiplying quantized coefficient data by the first multiplier generated by the first multiplier generation unit and the second multiplier generated by the second multiplier generation unit, wherein the quantized coefficient data is a result of quantization of a coefficient value for each frequency obtained by transforming image data based on an encoding system;

a shift unit that determines whether or not to perform a bit shift operation depending on the present encoding system, and when determined affirmatively, performs the bit shift operation to the data outputted from the multiplication unit according to the shift quantity data generated by the shift quantity generation unit; and

a pre-processing unit which includes an operation function that multiplies the quantized coefficient data by an integer and an operation function that adds an addend for a dead zone to the quantized coefficient data, selectively switches between data subjected to operation and data not subjected to operation and outputs the data in the operation of multiplying the quantized coefficient data by an integer and the operation of adding the addend to the quantized coefficient data respectively.

18. An inverse quantization method that adaptively handles performance of inverse quantization for plural encoding systems by selectively performing operations depending on a present encoding system from among the plural encoding systems, said method comprising:

a first multiplier generating step of generating a first multiplier, wherein the first multiplier generating step determines the first multiplier or a way of generating the first multiplier depending on the present encoding system;

a second multiplier generating step of generating a second multiplier, wherein the second multiplier generating step determines the second multiplier or a way of generating the second multiplier depending on the present encoding system;

a shift quantity generating step of generating shift quantity data indicating a bit shift quantity;

a multiplication processing step of determining whether or not to perform a multiplication operation depending on the present encoding system, and when determined affirmatively, performing the multiplication operation which comprises multiplying quantized coefficient data by the first multiplier generated in the first multiplier generating step and the second multiplier generated in the second multiplier generating step, wherein the quantized coefficient data is a result of quantization of a coefficient value for each frequency obtained by transforming image data based on an encoding system;

a shift processing step of determining whether or not to perform a bit shift operation depending on the present encoding system, and when determined affirmatively, performing the bit shift operation to the data outputted in the multiplication processing step according to the shift quantity data generated in the shift quantity generating step;

an addend generating step of generating an addend, wherein the addend generating step determines the addend or a way of generating the addend depending on the present encoding system; and

an addition processing step of determining whether or not to perform an addition operation depending on the present encoding system, and when determined affirmatively, performs the addition operation which comprises adding the addend generated in the addend generating step to the data outputted in the multiplication processing step,

wherein the shift processing step performs the bit shift operation to the data outputted in the addition processing step or to the data outputted in the multiplication processing step depending on the present encoding system, according to the shift quantity data generated in the shift quantity generating step.