Digital differential signal transmitter for low supply voltage

• US 8,401,098 B2
• Filed: 07/14/2009
• Issued: 03/19/2013
• Est. Priority Date: 05/06/2009
• Status: Expired due to Fees

• Current Assignee: Postech Academy-Industry Foundation
• Original Assignee: Postech Academy-Industry Foundation
• Inventors: Bae, Jun Hyun, Park, Hong June
• Primary Examiner(s): Payne, David C.
• Assistant Examiner(s): Hassan, Sarah
• Application Number:
  US12/503,048
• Publication Number:
  US 20100284489A1
• Time in Patent Office: 1,344 Days
• Field of Search: 375/226, 375/260, 327/175
• US Class Current: 375/260
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 7/0091 Transmitter details

Abstract

A digital differential signal transmitter circuit for a low supply voltage. A phase correction circuit for correcting digital signals transmitted through two signal paths in such a way as to have a phase relationship of differential signals and duty cycle correction circuits for correcting the digital signals in such a way as to maintain signal integrity in spite of changes in process, supply voltage and temperature are installed on the two signal paths so that the distortion of digital differential signals is compensated for. Power consumption at a final output section of the transmitter circuit is reduced. Impedances of the transmitter circuit and transmission lines are matched so that the transmitter circuit can operate insensitively with respect to operation circumstances.

Claims

1. A digital differential signal transmitter circuit for a low supply voltage, comprising:

signal selection switches composed of multiplexers which are respectively installed on two signal paths to select and output to the respective signal paths any ones of input differential signals and clock signals;

a differential phase correction circuit arranged between the two signal paths to be inputted with signals outputted from the two signal paths, delay output timing and correct a phase difference between two signals;

duty cycle correction circuits configured to detect edges of signals transmitted from the respective signal paths after phase correction is implemented, generate pulses, and control a switch for increasing and decreasing an output signal by the pulses so that duty cycles of signals outputted from the respective signal paths are corrected to be constant; and

a final output section configured to match an impedance of an output driver using a reference resistor having the same impedance as transmission lines for transmitting the input differential signals to a receiver, and output the input differential signals corrected in duty cycles to the transmission lines,

wherein the signal selection switches are configured to output the clock signals while phase difference correction and duty cycle correction are implemented in response to a correction function activation signal.

15. The digital differential signal transmitter circuit according to claim 1, wherein the final output section comprises:

an impedance matching calibration circuit having a pull-up calibration unit which calibrates an impedance of a pull-up part arranged in an output driver using a reference resistor having the same impedance as the transmission lines, and a pull-down calibration unit which calibrates an impedance of a pull-down part using the calibrated impedance of the pull-up part to be the same as the calibrated impedance of the pull-up part; and

an output driver configured to transmit signals having undergone phase correction and duty cycle correction through transmission lines, and having four switches which comprise NMOS transistors and variable resistors which are calibrated by the impedance matching calibration circuit.

18. The digital differential signal transmitter circuit according to claim 1, wherein the differential phase correction circuit comprises variable delays which are inputted with and delay signals outputted from the signal selection switches on the two signal paths, respectively, such that two signals have a phase difference of 180°

.

2. A digital differential signal transmitter circuit for a low supply voltage, comprising:

signal selection switches composed of multiplexers which are respectively installed on two signal paths to select and output to the respective signal paths any ones of input differential signals and clock signals;

a differential phase correction circuit arranged between the two signal paths to be inputted with signals outputted from the two signal paths, delay output timing and correct a phase difference between two signals;

duty cycle correction circuits configured to detect edges of signals transmitted from the respective signal paths after phase correction is implemented, generate pulses, and control a switch for increasing and decreasing an output signal by the pulses so that duty cycles of signals outputted from the respective signal paths are corrected to be constant; and

a final output section configured to match an impedance of an output driver using a reference resistor having the same impedance as transmission lines for transmitting the input differential signals to a receiver, and output the input differential signals corrected in duty cycles to the transmission lines,

wherein the differential phase correction circuit comprises variable delays which are inputted with and delay signals outputted from the signal selection switches on the two signal paths, respectively, such that two signals have a phase difference of 180°

,

wherein the differential phase correction circuit further comprises a phase controller which is fed back with signals outputted from the duty cycle correction circuits and generates control codes for the variable delays.

3. The digital differential signal transmitter circuit according to claim 2, wherein the variable delays are provided for respective signal paths, one of the variable delays increases a delay time of an output signal by one control code outputted from the phase controller, and the other of the variable delays decreases a delay time of an output signal by the other control code having complementariness with respect to the one control code.

4. The digital differential signal transmitter circuit according to claim 2, wherein the duty cycle correction circuit comprises:

edge detectors configured to detect rising edges of signals inputted from the differential phase correction circuit and generate pulses;

MOS switches composed of a PMOS switch which increases an output signal to be transmitted to the final output section using the pulses generated by the edge detectors and an NMOS switch which decreases an output signal to be transmitted to the final output section using the pulses;

a cross-coupled inverter connected to an output terminal which is commonly connected to the PMOS switch and the NMOS switch; and

a control circuit having a comparator and a counter which control a delay time to be delayed in the edge detectors so that a duty cycle of a final output in the transmitter circuit becomes 50%.

5. The digital differential signal transmitter circuit according to claim 4, wherein the edge detectors comprise:

a first edge detector having a buffer which receives a signal inputted from the differential phase correction circuit, and a NAND gate which has one input terminal to which an output of the buffer is directly inputted and the other input terminal to which the output of the buffer is inputted via inverters; and

a second edge detector having a delay element which is commonly connected to an input terminal of the buffer and receives the signal inputted from the differential phase correction circuit, and a NAND gate which has one input terminal to which an output of the delay element is directly inputted and the other input terminal to which the output of the delay element is inputted via inverters.

6. The digital differential signal transmitter circuit according to claim 5,

wherein the PMOS switch has a gate to which a signal outputted from the first edge detector is applied, one terminal which is connected to a power source and the other terminal which is connected to an output terminal of the duty cycle correction circuit, and

wherein the NMOS switch has a gate to which a signal outputted from the second edge detector is applied, one terminal which is connected to the other terminal of the PMOS switch so as to be connected to the output terminal of the duty cycle correction circuit and the other terminal which is connected to a ground source.

7. The digital differential signal transmitter circuit according to claim 6, wherein the control circuit compares a VTT/2 voltage corresponding to a 50% duty cycle of the final output outputted from the transmitter circuit and an average voltage of the final output calculated using a low pass filter, and controls the delay time to be delayed in the edge detectors so that a duty cycle of the final output of the transmitter circuit becomes 50%.

8. The digital differential signal transmitter circuit according to claim 7, wherein an output terminal of the counter is connected to the delay element which is provided in the second edge detector.

16. The digital differential signal transmitter circuit according to claim 2, wherein the final output section comprises:

an impedance matching calibration circuit having a pull-up calibration unit which calibrates an impedance of a pull-up part arranged in an output driver using a reference resistor having the same impedance as the transmission lines, and a pull-down calibration unit which calibrates an impedance of a pull-down part using the calibrated impedance of the pull-up part to be the same as the calibrated impedance of the pull-up part; and

an output driver configured to transmit signals having undergone phase correction and duty cycle correction through transmission lines, and having four switches which comprise NMOS transistors and variable resistors which are calibrated by the impedance matching calibration circuit.

17. The digital differential signal transmitter circuit according to claim 3, wherein the final output section comprises:

an impedance matching calibration circuit having a pull-up calibration unit which calibrates an impedance of a pull-up part arranged in an output driver using a reference resistor having the same impedance as the transmission lines, and a pull-down calibration unit which calibrates an impedance of a pull-down part using the calibrated impedance of the pull-up part to be the same as the calibrated impedance of the pull-up part; and

an output driver configured to transmit signals having undergone phase correction and duty cycle correction through transmission lines, and having four switches which comprise NMOS transistors and variable resistors which are calibrated by the impedance matching calibration circuit.

9. A digital differential signal transmitter circuit for a low supply voltage, comprising:

signal selection switches composed of multiplexers which are respectively installed on two signal paths to select and output to the respective signal paths any ones of input differential signals and clock signals;

a differential phase correction circuit arranged between the two signal paths to be inputted with signals outputted from the two signal paths, delay output timing and correct a phase difference between two signals;

duty cycle correction circuits configured to detect edges of signals transmitted from the respective signal paths after phase correction is implemented, generate pulses, and control a switch for increasing and decreasing an output signal by the pulses so that duty cycles of signals outputted from the respective signal paths are corrected to be constant; and

a final output section configured to match an impedance of an output driver using a reference resistor having the same impedance as transmission lines for transmitting the input differential signals to a receiver, and output the input differential signals corrected in duty cycles to the transmission lines,

wherein the final output section comprises;

an impedance matching calibration circuit having a pull-up calibration unit which calibrates an impedance of a pull-up part arranged in an output driver using a reference resistor having the same impedance as the transmission lines, and a pull-down calibration unit which calibrates an impedance of a pull-down part using the calibrated impedance of the pull-up part to be the same as the calibrated impedance of the pull-up part; and

an output driver configured to transmit signals having undergone phase correction and duty cycle correction through transmission lines, and having four switches which comprise NMOS transistors and variable resistors which are calibrated by the impedance matching calibration circuit.

10. The digital differential signal transmitter circuit according to claim 9, wherein the pull-up calibration unit comprises:

a reference resistor having the same impedance as the transmission lines and serving as a reference for impedance matching;

a comparator configured to compare an external reference signal with a voltage of one end of the reference resistor;

a pull-up matching counter configured to generate a pull-up control signal for adjusting a value of a variable resistor provided to the pull-up part using an output of the comparator and thereby implement impedance matching;

a first half-replica comprising a variable resistor which is commonly connected to an output terminal of the pull-up matching counter, is inputted with the pull-up control signal and is adjusted in impedance to be the same as that of the pull-up part; and

a transistor having one terminal to which the variable resistor constituting the first half-replica is connected, the other terminal to which the reference resistor is connected and a drain which is connected to the power source.

11. The digital differential signal transmitter circuit according to claim 10, wherein the pull-up control signal as an output of the pull-up matching counter is commonly applied to the variable resistor provided to the pull-up part and the first half-replica, the reference resistor is provided between the transistor and the ground source, and the variable resistor constituting the first half-replica is provided between a power supply source VTT and the transistor.

12. The digital differential signal transmitter circuit according to claim 11, wherein the pull-down calibration unit comprises:

a second half-replica comprising a variable resistor which is adjusted in impedance by the pull-up control signal in the same manner as in the pull-up part so that an impedance of the pull-down part becomes the same as the calibrated impedance of the pull-up part;

a comparator;

a pull-down matching counter configured to generate a pull-down control signal for adjusting a value of a variable resistor provided to the pull-down part using an output of the comparator and thereby implement impedance matching;

a third half-replica comprising a variable resistor which is commonly connected to an output terminal of the pull-down matching counter, is inputted with the pull-down control signal and is adjusted in impedance to be the same as the pull-down part; and

transistors arranged between the second half-replica and the third half-replica.

13. The digital differential signal transmitter circuit according to claim 12, wherein the pull-down control signal PD_CTRL is commonly applied to the variable resistor provided to the pull-down part and the third half-replica, the second half-replica is arranged between the power supply source VTT and one terminal of one transistor, the third half-replica is arranged between the other terminal of the other transistor and the ground source, and a common terminal of two transistors, which are provided between the second and third half-replicas, is connected to an input terminal of the comparator to be compared with the external reference signal.

14. The digital differential signal transmitter circuit according to claim 9, wherein the output driver is configured to output input signals, which are driven with an amplitude measured between a first source VDD and a second source VSS, as output signals, which are centered on 0.5×

VTT and have a maximum value of 0.75×

VTT and a minimum value of 0.25×

VTT so as to have an amplitude of 0.5×

VTT.

19. The digital differential signal transmitter circuit according to claim 9, wherein the differential phase correction circuit comprises variable delays which are inputted with and delay signals outputted from the signal selection switches on the two signal paths, respectively, such that two signals have a phase difference of 180°

.

20. The digital differential signal transmitter circuit according to claim 9, wherein the signal selection switches are configured to output the clock signals while phase difference correction and duty cycle correction are implemented in response to a correction function activation signal.