Apparatus, computer program product and associated methodology for video analytics
First Claim
Patent Images
1. A processor for video analytics comprising:
- a plurality of registers each partitioned into at least two fields, each field being configured to store pixel data corresponding to an individual pixel;
an instruction decoder configured to decode SIMD instructions from a predetermined SIMD instruction set, the predetermined SIMD instruction set including at least a splice instruction, an averaging instruction and a half subtraction instruction, the splice instruction combining pixels from a single row to generate a pixel matrix having more than one row;
an arithmetic-logic unit configured to perform operations corresponding to the decoded SIMD instructions on each of the plurality of registers, each operation being simultaneously performed on each field in a register without causing carry bits to bleed from one field in the register to an adjacent field in the register;
an I/O unit configured to interface with at least one external device and configured to receive data from and transmit data to the external device; and
a data bus configured to interconnect the plurality of registers, the arithmetic-logic unit and the I/O unit.
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Abstract
A processor and associated methodology employ a SIMD architecture and instruction set to efficiently perform video analytics operation on images. The processor contains a group of SIMD instructions used by the method to implement video analytic filters that avoid bit expansion of the pixels to be filtered. The filters hold the number of bits representing a pixel constant throughout the entire operation, conserving processor capacity and throughput when performing video analytics.
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Citations
17 Claims
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1. A processor for video analytics comprising:
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a plurality of registers each partitioned into at least two fields, each field being configured to store pixel data corresponding to an individual pixel; an instruction decoder configured to decode SIMD instructions from a predetermined SIMD instruction set, the predetermined SIMD instruction set including at least a splice instruction, an averaging instruction and a half subtraction instruction, the splice instruction combining pixels from a single row to generate a pixel matrix having more than one row; an arithmetic-logic unit configured to perform operations corresponding to the decoded SIMD instructions on each of the plurality of registers, each operation being simultaneously performed on each field in a register without causing carry bits to bleed from one field in the register to an adjacent field in the register; an I/O unit configured to interface with at least one external device and configured to receive data from and transmit data to the external device; and a data bus configured to interconnect the plurality of registers, the arithmetic-logic unit and the I/O unit. - View Dependent Claims (2, 3, 4, 5)
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6. A filtering method for video analytics using an n-pixel by n-pixel filter, the filtering method comprising:
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packing a source image including a plurality of pixels into a plurality of registers, each of said plurality of registers being partitioned into at least two fields, each field corresponding to a single pixel, and each pixel including a predetermined number of bits; applying, in a data processor, an n-pixel by n-pixel filter kernel to the plurality of registers using SIMD instructions to generate a plurality of partial results, said SIMD instructions including at least a splice instruction, an averaging instruction and a half subtraction instruction, the splice instruction combining pixels from a single row to generate a pixel matrix having more than one row; combining the partial results, in a data processor, using SIMD instructions to generate a final result; and outputting the final result to at least one of a display and an electronic storage medium, wherein the predetermined number of bits is held constant throughout the filtering method. - View Dependent Claims (7, 8)
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9. A method of performing video analytics comprising:
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partitioning a register into at least two fields; packing a pixel, including a predetermined number of bits, into each field of the register; and performing SIMD instructions on the entire register, the SIMD instructions corresponding to a predefined SIMD instruction set including at least a splice instruction, an averaging instruction and a half subtraction instruction, wherein the splice instruction combines pixels from a single row to generate a pixel matrix having more than one row. - View Dependent Claims (10)
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11. A processor for video analytics comprising:
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means for storing pixel data contiguously; means for decoding SIMD instructions from a predetermined SIMD instruction set, the SIMD instruction set including at least a splice instruction, an averaging instruction and a half subtraction instruction, the splice instruction combining pixels from a single row to generate a pixel matrix having more than one row; means for performing operations, corresponding to the decoded instructions, simultaneously on the contiguously stored pixel data, each pixel data contiguously stored being insulated from carry bits of other pixel data contiguously stored; means for receiving data from an external device, and means for transmitting data to an external device. - View Dependent Claims (12, 13, 14)
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15. A non-transitory computer-readable storage medium having computer-readable instructions stored thereon, the computer-readable instruction when executed by a computer cause the computer to perform the steps comprising:
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partitioning each register of a plurality of registers into a plurality of fields, each register including at least two fields; packing a source image including a plurality of pixels into the plurality of registers, each field corresponding to a single pixel, each pixel including a predetermined number of bits; applying an n-pixel by n-pixel filter kernel to the plurality of registers using SIMD instructions to generate a plurality of partial results, said SIMD instructions including at least a splice instruction, an averaging instruction and a half subtraction instruction, the splice instruction combining pixels from a single pixel row to generate a pixel matrix having more than one row; combining the partial results, in a data processor, using the SIMD instructions to generate a final result; and outputting the final result to at least one of a display and an electronic storage medium, wherein the predetermined number of bits of each pixel is held constant in the applying step and the combining step. - View Dependent Claims (16, 17)
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Specification