Techniques for reducing memory write operations using coalescing memory buffers and difference information

• US 8,402,184 B2
• Filed: 03/07/2011
• Issued: 03/19/2013
• Est. Priority Date: 11/24/2006
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Danilak, Radoslav
• Primary Examiner(s): SONG, HUA JASMINE
• Application Number:
  US13/042,231
• Publication Number:
  US 20120054415A1
• Time in Patent Office: 743 Days
• Field of Search: 711/100, 711/103, 711/154, 711/170, 711/E12.001, 711/E12.008, 711/E12.009, 710/52, 710/56
• US Class Current: 710/56
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

Techniques are described for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information is stored in coalescing memory buffers. To this end, the write operations may be reduced, utilizing the difference information.

Claims

1. An apparatus comprising:

a difference computation module;

one or more coalescing memory buffers;

wherein the difference computation module is enabled to

receive from a host processor a command initiating an operation to be applied to storage devices,

identify the operation as a write operation directed to one or more of a plurality of blocks of the storage devices,

reconstruct a current state of data of the one or more blocks,

compute a difference between the current state and a state that would result from the write operation, and

populate at least one of the coalescing memory buffers with difference information associated with the difference and to be used to update an associated one of the blocks;

wherein the coalescing memory buffers are separate from the storage devices; and

wherein the difference computation module is further enabled to determine whether the coalescing memory buffers are full, and to selectively write the difference information in the coalescing memory buffers to the storage devices, based on the determination of whether the coalescing memory buffers are full.

2. The apparatus of claim 1, wherein the apparatus is coupled between the host processor and the storage devices.

3. The apparatus of claim 2, further comprising at least some of the storage devices.

4. The apparatus of claim 1, wherein the apparatus is coupled between the host processor and secondary storage.

5. The apparatus of claim 1, wherein the difference information includes a location of the write operation.

6. The apparatus of claim 5, wherein the difference information does not include data of the write operation.

7. An apparatus comprising:

a difference computation module;

one or more coalescing memory buffers;

wherein the difference computation module comprises

means for receiving from a host processor a command initiating an operation to be applied to storage devices,

means for identifying the operation as a write operation directed to one or more of a plurality of blocks of the storage devices,

means for reconstructing a current state of data of the one or more blocks,

means for computing a difference between the current state and a state that would result from the write operation, and

means for populating at least one of the coalescing memory buffers with difference information associated with the difference and to be used to update an associated one of the blocks; and

wherein the coalescing memory buffers are separate from the storage devices; and

wherein the difference computation module further comprises means for determining whether the coalescing memory buffers are full, and to selectively write the difference information in the coalescing memory buffers to the storage devices, based on the determination of whether the coalescing memory buffers are full.

8. The apparatus of claim 7, wherein the apparatus is coupled between the host processor and the storage devices.

9. The apparatus of claim 8, further comprising at least some of the storage devices.

10. The apparatus of claim 7, wherein the apparatus is coupled between the host processor and secondary storage.

11. The apparatus of claim 7, wherein the difference information includes a location of the write operation.

12. The apparatus of claim 11, wherein the difference information does not include data of the write operation.