Systems and methods for storing data in a multi-level cell solid state storage device

• US 8,402,203 B2
• Filed: 12/31/2009
• Issued: 03/19/2013
• Est. Priority Date: 12/31/2009
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Strope, Todd Ray
• Primary Examiner(s): Dudek, Jr., Edward
• Assistant Examiner(s): Fishburn, John P
• Application Number:
  US12/650,712
• Publication Number:
  US 20110161556A1
• Time in Patent Office: 1,174 Days
• Field of Search: 711/103, 711/E12.008
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies

Abstract

This disclosure is related to systems and methods for storing data in multi-level cell solid state storage devices, such as Flash memory devices. In one example, a multi-level cell memory array has programmable pages, a first page having a first programming time, and a second page having a second programming time that is different than the first programming time. In one embodiment, the first programming time is faster than the second programming time. Further, a controller coupled to the multi-level cell memory array may be configured to select the first page to store the data when a priority level of a write operation indicates a first priority level and select the second page to store the data when the priority level indicates a second priority level.

Claims

1. A device comprising:

a first memory adapted to store a map that includes a list of pages of a multi-level cell solid state memory and an indicator of a priority level associated with each of the pages, each indicator of the priority level in the map being one of at least two different priority levels that correspond to two different page programming times; and

a controller configured to;

receive a write request for data to be stored in a multi-level cell solid state memory;

determine a priority level of the write request;

select a page of the pages based on the indicator associated with the page in the list of pages and based on the determined priority level of the write request; and

store at least a portion of the data associated with the write request in the selected page.

2. The device of claim 1 wherein the at least two different priority levels comprise a first priority level and a second priority level, and wherein the pages of the multi-level cell solid state memory comprise at least a first page having a first programming time of the two different page programming times and a second page having a second programming time of the two different page programming times, and wherein, in the map, the first page is associated with the first priority level and the second page is associated with the second priority level, and wherein the controller is further configured to:

select the first page based on the indicator associated with the first page when the priority level of the write request indicates a first priority level;

select the second page based on the indicator associated with the second page when the priority level of the write request indicates a second priority level.

3. The device of claim 2 wherein the first programming time is faster than the second programming time, the first priority level in the map is designated as higher than the second priority level in the map, and the first page is selected to store data associated with the first priority level of the received write request due to the first programming time being faster than the second programming time.

4. The device of claim 1, and further comprising a host interface, wherein the controller is configured to receive the write request from a host device through the host interface.

5. The device of claim 2 further comprising the controller adapted to generate the map by determining, for each of the pages, the first programming time or the second programming time and storing the respective indicator of the priority level based on the determination of the first programming time or the second programming time in the map.

6. The device of claim 5 wherein determining the first programming time or the second programming time comprises programming a respective page of the pages and measuring an amount of time for programming the respective page.

7. The device of claim 2 further comprising determining an amount of time for programming for each of the pages of the multi-level solid state memory and selecting the indicator of the priority level to be stored in the map for each page based on the amount of time.

8. The device of claim 7 wherein the indicator of the priority level in the map comprises a single bit, where a first state of the single bit represents the first priority level and a second state of the single bit represents the second priority level.

9. The device of claim 7 further comprising more than two priority levels and the indicator comprises more than one bit.

10. The device of claim 2, wherein the multi-level cell solid state memory comprises a cell configured to store more than one bit of information in a given physical programming page, and wherein the first page comprises a first logical page addressed to the given physical programming page and the second page comprises a second logical page addressed to the given physical programming page.

11. The device of claim 10, wherein the controller is configured to store the at least a portion of the data by:

using the given physical programming page in the multi-level cell solid state memory by applying a first voltage to the given physical programming page, when the first page is selected; and

using the given physical programming page in the multi-level cell solid state memory by applying a second voltage, that is different than the first voltage, to the given physical programming page, when the second page is selected.

12. The device of claim 1 wherein the multi-level solid state memory comprises multi-level cell (MLC) NAND Flash memory.

13. The device of claim 2 further comprising storing data for a plurality of write requests other than the received write request only in those of the pages associated with the first priority level in the map and not storing the data for the plurality of write requests in those of the pages associated with the second priority level in the map.

14. The device of claim 13 further comprising moving data from those of the pages associated with the first priority level in the map to pages associated with the second priority level in the map during background operations of the device.

15. The device of claim 1 wherein the priority level of the received write request is determined based on a type of data, an indicator from the host, an amount of buffer space filled, or a fill rate of a buffer.

16. The device of claim 2 further comprising the controller adapted to receive an indicator of a user selectable setting to initially store all data to those of the pages associated with the first priority level in the map.

17. A non-transitory storage medium storing instructions to cause a processor to perform a method comprising:

storing a list of pages and an indicator of a priority level associated with each page, the pages including at least first and second pages of a multi-level cell memory;

receiving a request for a write operation;

determining a priority level of the write operation;

selecting the first page based on the indicator associated with the first page when the priority level of the write operation indicates a first priority level;

selecting the second page based on the indicator associated with the second page when the priority level of the write operation indicates a second priority level; and

storing the data associated with the write operation in the selected page.

18. The non-transitory storage medium of claim 17 wherein the first page has a first programming time, and the second page has a second programming time that is slower than the first programming time.

19. The non-transitory storage medium of claim 17 having instructions to cause a processor to perform the method further comprising:

generating the list of the pages by determining an amount of time for programming for each page of at least one even block and one odd block of the multi-level cell memory and selecting the indicator of the priority level to be stored for each of the pages based on the amount of time.

20. The non-transitory storage medium of claim 17, wherein storing comprises:

using a given physical programming page in the multi-level cell memory to store the data by applying a first voltage to the given physical programming page, when the first page is selected to store the data; and

using the given physical programming page in the multi-level cell memory to store the data by applying a second voltage, that is different than the first voltage, to the given physical programming page, when the second page is selected to store the data.

21. The non-transitory storage medium of claim 20, wherein the given physical programming page comprises a cell of the multi-level cell memory configured to store more than one bit of information.

22. The non-transitory storage medium of claim 21, wherein the first page comprises a first logical page addressed to the given physical programming page and the second page comprises a second logical page addressed to the given physical programming page.