Alteration of execution of a program in response to an execution-optimization information

• US 8,402,257 B2
• Filed: 11/30/2005
• Issued: 03/19/2013
• Est. Priority Date: 08/29/2005
• Status: Expired due to Fees

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Hillis, W. Daniel, Mangione-Smith, William Henry, Myhrvold, Nathan P., Tegreene, Clarence T., Wood, Lowell L. Jr.
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US11/292,296
• Publication Number:
  US 20070050607A1
• Time in Patent Office: 2,666 Days
• Field of Search: 712/227
• US Class Current: 712/227
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 8/443 Optimisation

Abstract

Embodiments include a device, and a method. In an embodiment, a device includes an information store operable to save an execution-optimization information, a first processor, and a hardware circuit. The hardware circuit includes a hardware circuit for altering an execution of a program by the first processor in response to the execution-optimization information. The execution-optimization information created by a hardware device utilizing data collected from a second processor and corresponding to a previous runtime execution by the second processor of at least a portion of the program that was transparent to any software executing on the second processor.

Claims

1. A method comprising:

identifying an instruction to be fetched for execution by a first processor; and

altering an execution of the instruction to be fetched for execution in response to an execution-optimization information,

the execution-optimization information previously generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor, the hardware device optimizing data handling by class of program data, wherein altering an execution of the instruction to be fetched for execution in response to an execution-optimization information includes altering an execution of the instruction by the hardware device by at least one of deleting, replacing, modifying or adding instructions, and altering a movement of program data with respect to the first processor, wherein the instruction to be fetched for execution by the first processor is included in a program of instructions and execution of the program operates on the program data, wherein the execution-optimization information optimizes data handling by class of program data, and wherein at least one class of program data includes data items having at least one extra bit on an end of the data items that indicates a nature of the data items, and wherein the execution-optimization information is at least partially based on a comparison of an execution of at least one instruction pursuant to a first resource management policy and an execution of the least one instruction pursuant to a second resource management policy, the first resource management policy being an optimistic policy that assumes based on at least one of theoretical information or historical information that the least one instruction will execute in a substantially optimal manner, and the second resource management policy being a pessimistic policy that assumes based on at least one of theoretical information or historical information that the least one instruction will execute in a substantially sub-optimal manner.

2. The method of claim 1, wherein the identifying an instruction to be fetched for execution by a first processor includes

identifying an instruction to be fetched from an instruction set of a static program for execution by a first processor.

3. The method of claim 1, wherein the altering an execution of the instruction to be fetched for execution in response to an execution-optimization information includes

altering an execution of the instruction to be fetched from an instruction set of a static program for execution in response to an execution-optimization information.

4. The method of claim 1, wherein the execution-optimization information generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor includes

information having been previously generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor, the second processor being at least a substantially same processor as the first processor.

5. The method of claim 1, wherein the execution-optimization information generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor includes

information having been previously generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor, the second processor being at least a substantially different processor from the first processor.

6. The method of claim 1, wherein the execution-optimization information generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor includes

information having been previously generated by a hardware device utilizing data corresponding to a state of the second processor during a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor.

7. The method of claim 1, wherein the execution-optimization information generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor includes

information having been previously generated by a hardware device utilizing data corresponding to an instruction state during a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor.

8. The method of claim 1, wherein the execution-optimization information generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor includes

information having been previously generated by a hardware device utilizing data corresponding to a data relationship during a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor.

9. The method of claim 1, wherein altering an execution of the instruction to be fetched for execution in response to an execution-optimization information includes altering of a movement of program data with respect to the first processor.

10. The method of claim 9, wherein altering of a movement of program data with respect to the first processor includes

saving program data in a location that substantially optimizes use of the program data by the instruction to be fetched for execution.

11. A device comprising:

means for identifying an instruction to be fetched from an instruction set of a program for execution by a first processor; and

means for altering an execution of the instruction from the instruction set of a program in response to an execution-optimization information by at least one of deleting, replacing, modifying or adding instructions to the instruction set of the program, and for altering a movement of data with respect to the first processor in response to the execution-optimization information,

the execution-optimization information having been generated by a hardware device utilizing data generated by a second processor, and which data corresponds to a previous real execution the instruction to be fetched from the instruction set of a program that was transparent to software executing on the second processor, wherein the execution-optimization information optimizes data handling by class of data, and wherein at least one class of data includes data items having at least one extra bit on an end of the data items that indicates a nature of the data items, and wherein at least one of the means for identifying an instruction and the means for altering an execution of the instruction are at least partially implemented in hardware, and wherein the execution-optimization information is at least partially based on a comparison of an execution of at least one instruction pursuant to a first resource management policy and an execution of the least one instruction pursuant to a second resource management policy, the first resource management policy being an optimistic policy that assumes based on at least one of theoretical information or historical information that the least one instruction will execute in a substantially optimal manner, and the second resource management policy being a pessimistic policy that assumes based on at least one of theoretical information or historical information that the least one instruction will execute in a substantially sub-optimal manner.