Multi-chip reticle photomasks

• US 8,404,430 B2
• Filed: 08/01/2011
• Issued: 03/26/2013
• Est. Priority Date: 06/12/2009
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Anderson, Brent Alan, Rankin, Jed Hickory
• Primary Examiner(s): ROSASCO, STEPHEN D
• Application Number:
  US13/195,307
• Publication Number:
  US 20110287349A1
• Time in Patent Office: 603 Days
• Field of Search: 430/5, 430/311, 430/312, 430/313, 430/322, 716 50- 56
• US Class Current: 430/312
• CPC Class Codes: G03F 1/26 Phase shift masks [PSM]; PSM blanks; Preparation thereof
• CPC Class Codes: G03F 1/50 Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof

Abstract

A multi-chip reticle, methods of designing and fabricating multi-chip reticles, a system for designing a multi-chip reticle, and a method of fabricating integrated circuit chips using the multi-chip reticle. The multi-chip reticle includes a transparent substrate having two or more separate chip images arranged in an array, each chip image of said two or more chip images having only one type of reticle image, wherein at least two of said two more chip images have different types of reticle images.

Claims

1. A method of forming an integrated circuit chip, comprising:

(a) loading a multi-chip reticle into a photolithographic exposure tool, said multi-chip reticle having two or more separate chip images arranged in an array, each chip image of said two or more chip images having only one type of reticle image, wherein at least two of said two more chip images have different types of reticle images;

after (a), (b) coating a semiconductor substrate with a photoresist layer, loading said substrate into said photolithographic exposure tool, exposing said first photoresist layer using a first chip image of said two or more chip images; and

after (b), (c) removing said substrate from said photolithography tool, developing said first photoresist layer, processing said substrate, removing said first photoresist layer, coating said semiconductor substrate with a second photoresist layer, loading said substrate into said photolithographic exposure tool, exposing said second photoresist layer using a second chip image of said two or more chip images, said second chip image having only one and a different type of reticle image than said first chip image, removing said substrate, developing said second photoresist layer, further processing said substrate and removing said second photoresist layer.

2. The method of claim 1, wherein said types of reticle images are selected from the group consisting of binary reticle images, positive phase shift reticle images, negative phase shift reticle images, attenuated phase shift reticle images, embedded attenuated phase shift reticle images, alternating phase shift reticle images and binary alternating phase shift reticle images.

3. The method of claim 1, wherein said processing and said further processing are independently selected from the group consisting of ion implantation, etching and deposition.

4. The method of claim 1, wherein each chip image of said two or more chip images define different fabrication levels of a same integrated circuit chip design.

5. The method of claim 1, wherein at least two chip images of said two or more chip images define a same fabrication level of integrated circuit chips of different design.

6. The method of claim 1, wherein at least two chip images of said two or more chip images in combination define a same fabrication level of a same integrated circuit chip design.

7. The method of claim 1, wherein said chip images define fabrication levels of a field effect transistor, said fabrication levels selected from the group consisting of trench dielectric isolation fabrication levels, gate fabrication levels, contact fabrication dielectric layers, metal wiring fabrication levels and via fabrication levels.

8. A method, comprising:

selecting fabrication levels from one or more integrated circuit designs;

generating a mask shape dataset for each selected fabrication level;

merging said mask shape datasets into a single multi-chip mask shape dataset representing two or more chip images, each chip image of said two or more chip images assigned only one type of reticle image, wherein at least two of said two more chip images are assigned different types of reticle images;

generating a set of mask writer datasets based on said multi-chip mask shape dataset and reticle image type of each chip image of said two or more chip images; and

wherein said generating said mask shape dataset, merging said mask shape datasets and generating said set of mask writer datasets are performed by processors of one or more computers.

9. The method of claim 8, further including:

fabricating a multi-chip reticle using said mask writer datasets, said multi-chip reticle comprising a transparent substrate having two or more separate chip images arranged in an array, each chip image of said two or more chip images having only one type of reticle image, wherein at least two of said two more chip images consist of different types of reticle images.

10. The method of claim 8, wherein said types of reticle images are selected from the group consisting of binary reticle images, positive phase shift reticle images, negative phase shift reticle images, attenuated phase shift reticle images, embedded attenuated phase shift reticle images, alternating phase shift reticle images and binary alternating phase shift reticle images.

11. The method of claim 8, wherein each chip image of said two or more chip images define different fabrication levels of a same integrated circuit chip design.

12. The method of claim 8, wherein at least two chip images of said two or more chip images define a same fabrication level of integrated circuit chips of different design.

13. The method of claim 8, wherein at least two chip images of said two or more chip images in combination define a same fabrication level of a same integrated circuit chip design.

14. The method of claim 8, wherein said chip images define fabrication levels of a field effect transistor, said fabrication levels selected from the group consisting of trench dielectric isolation fabrication levels, gate fabrication levels, contact fabrication dielectric layers, metal wiring fabrication levels and via fabrication levels.

15. A computer system including a computer comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit coupled to communicate with said processor, said memory unit containing instructions that when executed by the processor implement a method for designing a multi-chip reticle, said method comprising the computer implemented steps of:

selecting fabrication levels from one or more integrated circuit designs;

generating a mask shape dataset for each selected fabrication level;

merging said mask shape datasets into a single multi-chip mask shape dataset representing two or more chip images, each chip image of said two or more chip images assigned only one type of reticle image, wherein at least two of said two more chip images are assigned different types of reticle images; and

generating a set of mask writer datasets based on said multi-chip mask shape dataset and the reticle image type of each chip image of two or more chip images.

16. The computer system of claim 15, wherein said reticle images are selected from the group consisting of binary reticle images, positive phase shift reticle images, negative phase shift reticle images, attenuated phase shift reticle images, embedded attenuated phase shift reticle images, alternating phase shift reticle images and binary alternating phase shift reticle images.

17. The computer system of claim 15, wherein each chip image of said two or more chip images define different fabrication levels of a same integrated circuit chip design.

18. The computer system of claim 15, wherein at least two chip images of said two or more chip images define a same fabrication level of integrated circuit chips of different design.

19. The computer system of claim 15, wherein at least two chip images of said two or more chip images in combination define a same fabrication level of a same integrated circuit chip design.

20. The computer system of claim 15, wherein said chip images define fabrication levels of a field effect transistor, said fabrication levels selected from the group consisting of trench dielectric isolation fabrication levels, gate fabrication levels, contact fabrication dielectric layers, metal wiring fabrication levels and via fabrication levels.

21. A method of forming an integrated circuit chip, comprising:

(a) loading a multi-chip reticle into a photolithographic exposure tool, said multi-chip reticle having two or more separate chip images arranged in an array, each chip image of said two or more chip images having only one type of reticle image, wherein at least two of said two more chip images have different types of reticle images;

after (a), (b) coating a semiconductor substrate with a photoresist layer, loading said substrate into said photolithographic exposure tool, exposing said first photoresist layer using a first chip image of said two or more chip images; and

after (b), (c) exposing said first photoresist layer using a second chip image of said two or more chip images, said second chip image having only one and a different type of reticle image than said first chip image, removing said substrate, developing said first photoresist layer, processing said substrate and removing said first photoresist layer.

22. The method of claim 21, wherein said types of reticle images are selected from the group consisting of binary reticle images, positive phase shift reticle images, negative phase shift reticle images, attenuated phase shift reticle images, embedded attenuated phase shift reticle images, alternating phase shift reticle images and binary alternating phase shift reticle images.

23. The method of claim 21, wherein said processing and said further processing are independently selected from the group consisting of ion implantation, etching and deposition.

24. The method of claim 21, wherein each chip image of said two or more chip images define different fabrication levels of a same integrated circuit chip design.

25. The method of claim 21, wherein at least two chip images of said two or more chip images define a same fabrication level of integrated circuit chips of different design.

26. The method of claim 21, wherein at least two chip images of said two or more chip images in combination define a same fabrication level of a same integrated circuit chip design.

27. The method of claim 21, wherein said chip images define fabrication levels of a field effect transistor, said fabrication levels selected from the group consisting of trench dielectric isolation fabrication levels, gate fabrication levels, contact fabrication dielectric layers, metal wiring fabrication levels and via fabrication levels.