Enhancement mode GaN HEMT device and method for fabricating the same

• US 8,404,508 B2
• Filed: 04/08/2010
• Issued: 03/26/2013
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Efficient Power Conversion Corporation
• Original Assignee: Efficient Power Conversion Corporation
• Inventors: Lidow, Alexander, Beach, Robert, Nakata, Alana, Cao, Jianjun, Zhao, Guang Yuan
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US12/756,960
• Publication Number:
  US 20100258843A1
• Time in Patent Office: 1,083 Days
• Field of Search: 438 46- 52, 438172-177, 438285-299, 438/481, 257/E21.409, 257/E29.074, 257/89, 257/91, 257/194, 257/242, 257/246, 257/252, 257/315
• US Class Current: 438/46
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.

Claims

1. A method of forming an enhancement mode GaN transistor, the method comprising:

nucleating and growing transition layers on a substrate;

growing an III Nitride EPI layer over the transistor layers;

growing an III Nitride barrier layer over the EPI layer;

growing a GaN layer with acceptor type dopants over the barrier layer;

depositing a gate contact layer on the doped GaN layer;

applying a gate photo resistant pattern;

etching away the gate contact layer outside the gate region;

etching away the doped GaN layer, except a portion of the doped GaN layer beneath the gate contact;

removing the gate photo resistant pattern;

depositing a dielectric layer;

applying a contact photo resistant pattern;

etching the dielectric layer to open the drain and source contact area;

removing the contact photo resistant pattern;

depositing an Ohmic contact metal;

applying a metal photo resistant pattern;

etching the Ohmic contact metal;

removing the metal photo resistant pattern; and

performing rapid thermal annealing to form Ohmic drain and source contacts.

2. The method of claim 1, wherein the EPI layer is comprised of InAlGaN.

3. The method of claim 1, wherein the barrier layer is comprised of InAlGaN with a larger band gap than the buffer layer.

4. A method of forming an enhancement mode GaN transistor, the method comprising:

nucleating and growing transition layers on a substrate;

growing an InAlGaN EPI layer over the transistor layers;

growing an InAlGaN barrier layer over the InAlGaN EPI layer;

growing an InAlGaN layer with acceptor type dopants over the InAlGaN barrier layer;

growing a GaN layer with acceptor type dopants over the doped InAlGaN layer;

depositing a gate contact layer on the doped GaN layer

applying a gate photo resistant pattern;

etching away the gate contact layer outside the gate region;

etching away the doped GaN layer and the doped InAlGaN layer, except for portions of the doped GaN layer and the doped InAlGaN layer beneath gate contact;

removing the gate photo resistant pattern;

depositing a dielectric layer;

applying a contact photo resistant pattern;

etching the dielectric layer to open the drain and source contact area;

removing the contact photo resistant pattern;

depositing an Ohmic contact metal;

applying a metal photo resistant pattern;

etching the Ohmic contact metal;

removing the metal photo resistant pattern; and

performing rapid thermal annealing to form Ohmic drain and source contacts.

5. A method of forming an enhancement mode GaN transistor, the method comprising:

nucleating and growing transition layers on a substrate;

growing an InAlGaN EPI layer over the transistor layers;

growing an AlGaN barrier layer over the InAlGaN EPI layer;

growing an AlGaN layer with acceptor type dopants over the AlGaN barrier layer;

growing a GaN layer with acceptor type dopants over the doped AlGaN layer;

depositing a gate contact layer on the doped GaN layer

applying a gate photo resistant pattern;

etching away the gate contact layer outside the gate region;

etching away the doped GaN layer, except for portions of the doped GaN layer and the doped AlGaN layer beneath gate contact;

removing the gate photo resistant pattern;

applying another photo resistant pattern;

etching the doped AlGaN layer such that the doped AlGaN extends outside the gate region towards the drain;

removing the photo resistant pattern;

depositing a dielectric layer;

applying a contact photo resistant pattern;

etching the dielectric layer to open the drain and source contact area;

removing the contact photo resistant pattern;

depositing an Ohmic contact metal;

applying a fourth photo resistant pattern;

etching the Ohmic contact metal

removing the fourth photo resistant pattern; and

performing rapid thermal annealing to form Ohmic drain and source contacts.