Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement

• US 8,404,550 B2
• Filed: 10/15/2010
• Issued: 03/26/2013
• Est. Priority Date: 11/30/2009
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Scheiper, Thilo, Beyer, Sven, Wei, Andy, Hoentschel, Jan
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US12/905,383
• Publication Number:
  US 20110127618A1
• Time in Patent Office: 893 Days
• Field of Search: 257/213, 257/288, 257/402, 257/403, 257/404, 257/408, 257/409, 257/410, 257/613, 257/616, 438/142, 438/197, 438/289, 438/290, 438/291
• US Class Current: 438/289
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.

Claims

1. A method, comprising:

introducing a well dopant species into said semiconductor region on the basis of an implantation mask;

introducing a diffusion blocking species into a semiconductor region of a P-channel transistor, wherein said diffusion blocking species is introduced by using said implantation mask;

forming a threshold adjusting semiconductor material on said semiconductor region, said semiconductor region comprising said diffusion blocking species;

forming a gate electrode structure on said threshold adjusting semiconductor material, said gate electrode structure comprising a gate dielectric material separating an electrode material of said gate electrode structure from a channel region in said threshold adjusting semiconductor material;

introducing dopants for drain and source extension regions and drain and source regions; and

annealing said P-channel transistor by using said diffusion blocking species to suppress dopant diffusion below said channel region.

2. The method of claim 1, further comprising annealing said semiconductor region prior to forming said threshold adjusting semiconductor material so as to stabilize said diffusion blocking species.

3. The method of claim 1, wherein said diffusion blocking species comprises fluorine.

4. The method of claim 1, wherein said diffusion blocking species comprises at least one of nitrogen and carbon.

5. The method of claim 1, further comprising forming a strain-inducing semiconductor alloy in said semiconductor region after forming said gate electrode structure.

6. The method of claim 5, wherein introducing said dopant for the drain and source regions is performed so as to position said dopants within said strain-inducing semiconductor alloy.

7. The method of claim 1, wherein forming said gate electrode structure comprises forming said gate dielectric material so as to include a high-k dielectric material and forming a metal-containing material on said gate dielectric material.

8. The method of claim 1, wherein said threshold adjusting semiconductor material is comprised of silicon and germanium.

9. The method of claim 5, wherein said strain-inducing semiconductor alloy is comprised of silicon and germanium.

10. A method of forming a P-channel transistor, the method comprising:

performing a first implantation process so as to incorporate a well dopant species into an active region of said P-channel transistor by using an implantation mask;

performing a second implantation process so as to incorporate a non-doping species into said active region;

performing an anneal process so as to activate said well dopant species and stabilize said non-doping species;

forming a semiconductor material on said active region;

forming a gate electrode structure on said semiconductor material; and

forming drain and source extension regions and drain and source regions in said active region adjacent to said gate electrode structure.

11. The method of claim 10, further comprising forming a strain-inducing semiconductor material in said active region after forming said gate electrode structure and prior to forming said drain and source regions.

12. The method of claim 10, wherein said second implantation process is performed by using said implantation mask.

13. The method of claim 10, wherein said non-doping species comprises fluorine.

14. The method of claim 10, wherein said gate electrode structure is formed so as to comprise a high-k dielectric material and a metal-containing material comprising a work function adjusting species.

15. The method of claim 10, further comprising forming a metal silicide on said drain and source regions and on said gate electrode structure.

16. A method, comprising:

introducing a diffusion blocking species into a semiconductor region of a P-channel transistor;

stabilizing said diffusion blocking species by annealing said semiconductor region;

after stabilizing said diffusion blocking species, forming a threshold adjusting semiconductor material on said semiconductor region, said semiconductor region comprising said diffusion blocking species;

forming a gate electrode structure on said threshold adjusting semiconductor material, said gate electrode structure comprising a gate dielectric material separating an electrode material of said gate electrode structure from a channel region in said threshold adjusting semiconductor material;

introducing dopants for drain and source extension regions and drain and source regions; and

annealing said P-channel transistor by using said diffusion blocking species to suppress dopant diffusion below said channel region.