Source/drain extension control for advanced transistors

• US 8,404,551 B2
• Filed: 12/03/2010
• Issued: 03/26/2013
• Est. Priority Date: 12/03/2010
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Ranade, Pushkar, Shifren, Lucian, Sonkusale, Sachin R.
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): CHOI, CALVIN Y
• Application Number:
  US12/960,289
• Publication Number:
  US 20120139051A1
• Time in Patent Office: 844 Days
• Field of Search: 438/290, 257/368, 257/402
• US Class Current: 438/290
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10¹⁹ atoms/cm³, or alternatively, less than one-quarter the dopant concentration of the source and the drain.

Claims

1. A method of forming a planar transistor on a semiconductor bulk substrate, comprising the steps of

implanting a highly doped screening layer on the semiconductor bulk substrate, the highly doped screening layer having a preselected dopant concentration and thickness;

forming a threshold voltage set region above and in contact with the highly doped screening layer, the threshold voltage set region having a preselected thickness, the threshold voltage set region being co-extensive with the screening layer, the threshold voltage set region having a preselected dopant concentration that is less than the dopant concentration of the highly doped screening layer;

forming a substantially undoped channel on the threshold voltage set region, the substantially undoped channel extending to a source and a drain, the substantially undoped channel being co-extensive with the screening layer and the threshold voltage set region, the substantially undoped channel having a selected thickness, the screening layer and the threshold voltage set region extending to the source and drain;

forming a gate on a transistor substrate;

implanting source/drain extensions into the substantially undoped channel between the source and the drain that have a dopant concentration of less than about 1×

10¹⁹ atoms/cm³.

2. A planar transistor having a source and a drain on a semiconductor substrate comprising:

a source;

a drain;

a substantially undoped channel extending to the source and drain;

a threshold voltage set region below the substantially undoped channel, the threshold voltage set region having a thickness, depth, and dopant concentration tailored for a specific threshold voltage, the threshold voltage set region being co-extensive with the undoped channel;

a highly doped screening layer positioned below the threshold voltage set region and the substantially undoped channel and co-extensive therewith, the screening layer having a higher dopant concentration than the threshold voltage set region;

a gate positioned over the substantially undoped channel on a transistor substrate; and

implanted source/drain extensions contacting the source and the drain that respectively extend under the gate, the implanted source/drain extensions having a dopant concentration of less than about 1×

10¹⁹ atoms/cm³.

3. A planar transistor having a source and a drain on a semiconductor substrate comprising:

a substantially undoped channel extending to a source having a dopant concentration and drain having a dopant concentration;

a threshold voltage set region below the substantially undoped channel, the threshold voltage set region having a thickness, depth, and dopant concentration tailored for a specific threshold voltage, the threshold voltage set region being co-extensive with the undoped channel;

a highly doped screening layer positioned below the threshold voltage set region and the substantially undoped channel and co-extensive therewith, the screening layer having a higher dopant concentration than the threshold voltage set region;

a gate positioned over the substantially undoped channel on a transistor substrate; and

implanted source/drain extensions contacting the source and the drain that respectively extend under the gate, the implanted source/drain extensions having a dopant concentration of less than one-quarter the dopant concentration of the respective source and drain.

4. The planar transistor of claim 3, wherein the dopant concentration of the implanted source/drain extensions is between one-quarter and one-twentieth of the dopant concentration of the respective source and drain.

5. A method of forming a transistor on a semiconductor substrate comprising the steps of

doping a substrate to adjust threshold voltage to establish a threshold voltage set region that extends laterally to a source and a drain, the threshold voltage set region having a thickness, depth, and dopant concentration tailored for a specific threshold voltage;

growing a substantially undoped channel after formation of the threshold voltage set region, the undoped channel extending to the source and the drain;

implanting a highly doped screening layer below the threshold voltage set region and the substantially undoped channel and coextensive therewith, the screening layer having a higher dopant concentration than the threshold voltage set region;

forming a gate having spacers above the substantially undoped channel;

implanting source/drain extensions into the substantially undoped channel below the spacers and in contact with the source and drain to yield a dopant concentration of less than about 1×

10¹⁹ atoms/cm³′

, while maintaining a dopant concentration of less than about 5×

10¹⁷ atoms/cm³ in a channel volume having a depth of at least 5 nanometers below the gate and extending between the implanted source/drain extensions, wherein the implanted source/drain extensions are formed without halo implants.

6. The method of claim 5 further wherein the substantially undoped channel is an epitaxial layer.

7. The method of claim 5 wherein the gate is less than or equal to 65 nanometers in length, and further comprising the step of forming sidewall spacers having a maximum width of less than 20 nanometers.

8. A transistor without halo implants comprising

an undoped channel extending to a source and a drain, with the source and the drain formed without halo implants;

a highly doped screening layer below the undoped channel and coextensive therewith;

a gate above the substantially undoped channel;

implanted source/drain extensions below the gate and extending toward each other from the source and the drain, the implanted source/drain extensions being processed post-implant to maintain a dopant concentration of less than about 5×

10¹⁷ atoms/cm³ in a channel volume extending between the implanted source/drain extensions, and wherein the implanted source/drain extensions are formed without halo implants.

9. The transistor of claim 8 further comprising a threshold voltage setting region between the highly doped screening layer and the undoped channel.

10. An electronic device comprising:

a die comprising a transistor having an undoped channel extending to a source and a drain, with the source and the drain formed without halo implants;

a highly doped screening layer below the undoped channel and coextensive therewith;

a gate above the substantially undoped channel, and

implanted source/drain extensions below the gate and extending toward each other from the source and the drain, the implanted source/drain extensions being processed post-implant to maintain a dopant concentration of less than about 5×

10¹⁷ atoms/cm³ in a channel volume extending between the implanted source/drain extensions, and wherein the implanted source/drain extensions are formed without halo implants.

11. A die comprising

a plurality of transistors, with at least one transistor having an undoped channel extending to a source and a drain;

a highly doped screening layer below the undoped channel and coextensive therewith;

a gate above the substantially undoped channel of the at least one transistor; and

implanted source/drain extensions below the gate and extending toward each other from the source and the drain of the at least one transistor, the implanted source/drain extensions being processed post-implant to maintain a dopant concentration of less than about 5×

10¹⁷ atoms/cm³ in a channel volume extending between the implanted source/drain extensions, and wherein the implanted source/drain extensions are substantially formed without halo implants.