Methods of forming nonvolatile memory devices having electromagnetically shielding source plates
First Claim
Patent Images
1. A method of forming a non-volatile memory device, comprising:
- forming a first interlayer insulating layer on a memory array having a plurality of strings of non-volatile memory cells therein at side-by-side locations in a semiconductor substrate, said plurality of strings of non-volatile memory cells comprising a row of ground select transistors, a plurality of rows of non-volatile memory cells and a row of string select transistors;
patterning the first interlayer insulating layer to define at least one source region contact opening therein that exposes at least one source region of a ground select transistor, and also define a plurality of drain region contact openings therein that expose respective drain regions of corresponding string select transistors;
depositing an electrically conductive layer that extends onto the first interlayer insulating layer and into the at least one source region contact opening and the plurality of drain region contact openings;
patterning the deposited electrically conductive layer into a source plate that covers the plurality of strings of non-volatile memory cells and into a plurality of bit line contact plugs;
forming a second interlayer insulating layer on the source plate and the plurality of bit line contact plugs;
patterning the second interlayer insulating layer to define a plurality of bit line contact openings therein that expose corresponding ones of the plurality of bit line contact plugs; and
forming a plurality of bit lines that extend on the second interlayer insulating layer and into the plurality of bit line contact openings.
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Abstract
Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including a cell array region, memory cell transistors disposed at the cell array region, bitlines disposed on the memory cell transistors, and a source plate disposed between the memory cell transistors and the bitlines to veil the memory cell transistors thereunder.
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Citations
21 Claims
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1. A method of forming a non-volatile memory device, comprising:
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forming a first interlayer insulating layer on a memory array having a plurality of strings of non-volatile memory cells therein at side-by-side locations in a semiconductor substrate, said plurality of strings of non-volatile memory cells comprising a row of ground select transistors, a plurality of rows of non-volatile memory cells and a row of string select transistors; patterning the first interlayer insulating layer to define at least one source region contact opening therein that exposes at least one source region of a ground select transistor, and also define a plurality of drain region contact openings therein that expose respective drain regions of corresponding string select transistors; depositing an electrically conductive layer that extends onto the first interlayer insulating layer and into the at least one source region contact opening and the plurality of drain region contact openings; patterning the deposited electrically conductive layer into a source plate that covers the plurality of strings of non-volatile memory cells and into a plurality of bit line contact plugs; forming a second interlayer insulating layer on the source plate and the plurality of bit line contact plugs; patterning the second interlayer insulating layer to define a plurality of bit line contact openings therein that expose corresponding ones of the plurality of bit line contact plugs; and forming a plurality of bit lines that extend on the second interlayer insulating layer and into the plurality of bit line contact openings. - View Dependent Claims (2, 3)
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4. A method of fabricating a semiconductor device, comprising:
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forming memory cell transistors on a semiconductor substrate, the memory cell transistors being disposed between source and drain electrodes to constitute a cell string; forming a source plate over the memory cell transistors, the source plate being connected to the source electrodes and having an opening over at least one of the drain electrodes; and forming a bitline structure over the source plate, the bitline structure being connected to the drain electrodes, wherein the source plate is formed to veil the memory cell transistors thereunder. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of fabricating a semiconductor device, comprising:
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forming a memory array comprising a plurality of strings of non-volatile memory cells located at side-by-side locations in a substrate, said plurality of strings of non-volatile memory cells comprising a row of ground select transistors; forming a plurality of bit lines electrically coupled to respective ones of the plurality of strings of non-volatile memory cells; and forming a source plate electrically coupled to source regions of the row of ground select transistors via a common source line which is formed a linear shape, and said source plate extending in two-dimensions over a plurality of word lines associated with each of the plurality of strings of non-volatile memory cells. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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Specification