Device and method for stopping an etching process

• US 8,404,597 B2
• Filed: 11/09/2007
• Issued: 03/26/2013
• Est. Priority Date: 11/09/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Brencher, Lothar, Meinhold, Dirk, Seidemann, Georg, Hartenberger, Michael, Dickenscheld, Wolfgang
• Primary Examiner(s): Tran, Binh X
• Application Number:
  US11/937,681
• Publication Number:
  US 20090124089A1
• Time in Patent Office: 1,964 Days
• Field of Search: 438/717, 438/720, 438/724, 438/742, 257/49, 257/69, 216/49, 216/69
• US Class Current: 438/714
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method including a step of etching the etch layer using a first etchant and a step of etching the intermediate layer using a second etchant. The first etchant includes a first etch selectivity of at least 5:1 with respect to the etch layer and the intermediate layer. The second etchant includes a second etch selectivity of at least 5:1 with respect to the intermediate layer and the stop layer. The first etchant being different from the second etchant.

Claims

1. A device for stopping an etching process, the device comprising:

an etch layer comprising a first material and an etch layer thickness;

an intermediate layer comprising a second material and an intermediate layer thickness; and

a stop layer comprising a third material, the stop layer having a stop layer thickness,

wherein the intermediate layer thickness is such that a ratio of the etch layer thickness to the intermediate layer thickness is at most 3 times a first etch selectivity for a fluorocarbon etchant between the first material and the second material,

wherein the first and second materials are such that the first etch selectivity for the fluorocarbon etchant between the first and second materials is at least a ratio of 5;

1,

wherein the second and third materials are such that a second etch selectivity for a fluoro-methane etchant between the second and third materials is at least a ratio of 5;

1, wherein the etch layer comprises an inclusion in a region to be etched for forming a via contact, and wherein the inclusion has an etching rate different than the etching rate of the first material when exposed to the fluorocarbon etchant.

2. The device of claim 1, wherein the second material comprises a dielectric material, wherein the etch layer comprises an oxide layer and the stop layer comprises a metal layer, and wherein the oxide layer and the metal layer are integrated in a metal-oxide-semiconductor (MOS) structure.

3. The device of claim 1, wherein the etch layer comprises non-uniformities with respect to the etch layer thickness or with respect to impurities within the first material.

4. The device of claim 1, wherein a stop layer thickness comprises a value within a range between 20 nm and 60 nm.

5. The device of claim 1, wherein the intermediate layer thickness is within a range of 10 nm to 50 nm.

6. The device of claim 1, wherein the stop layer and the etch layer extend into a further region, the stop layer and the etch layer comprising a direct contact in the further region.

7. The device of claim 1, wherein a stop layer thickness comprises a value within a range between 35 nm and 45 nm.

8. The device of claim 1, wherein the intermediate layer thickness is within a range of 20 nm to 30 nm.

9. The device of claim 1, wherein the stop layer is disposed over a substrate, wherein the intermediate layer is disposed over the stop layer, and wherein the etch layer is disposed over the intermediate layer.

10. The device of claim 1, wherein the intermediate layer thickness is less than a product of the second etch selectivity and the stop layer thickness.

11. A semiconductor structure comprising:

a stop layer of a first material disposed over a semiconductor substrate comprising an metallic layer, the stop layer having a stop layer thickness;

an intermediate layer of a second material disposed over the stop layer, the intermediate layer having an intermediate layer thickness; and

an etch layer of a third material disposed over the intermediate layer, the etch layer having an etch layer thickness,

wherein the intermediate layer thickness is such that a ratio of the etch layer thickness to the intermediate layer thickness is at most 3 times a first etch selectivity, wherein the first etch selectivity is the etching rate of the third material divided by an etching rate of the second material when exposed to a fluorocarbon etchant,

wherein the intermediate layer thickness is less than a product of a second etch selectivity with the stop layer thickness, wherein the second etch selectivity is the etching rate of the second material divided by an etching rate of the first material when exposed to a fluoro-methane etchant,

wherein the etch layer comprises an inclusion in a region to be etched for forming a via contact, and wherein the inclusion has an etching rate different than the etching rate of the third material when exposed to the fluorocarbon etchant.

12. The semiconductor structure of claim 11, wherein the etching rate of the inclusion is greater than the etching rate of the third material when exposed to a fluorocarbon etchant.

13. The semiconductor structure of claim 11, wherein the etching rate of the inclusion is less than the etching rate of the third material when exposed to a fluorocarbon etchant.

14. The semiconductor structure of claim 11, wherein the metallic layer comprises aluminum, wherein the first material comprises titanium nitride, wherein the second material comprises silicon oxynitride, and wherein the third material comprises an oxide material.

15. The semiconductor structure of claim 11, wherein the first and second materials are such that the first etch selectivity for the fluorocarbon etchant between the first and second materials is at least a ratio of 5:

1, and wherein the second and third materials are such that the second etch selectivity for a fluoro-methane etchant between the second and third materials is at least a ratio of 5;

1.

16. A semiconductor structure comprising:

a stop layer of a first material disposed over a semiconductor substrate comprising a metallic layer;

an intermediate layer of a second material disposed over the stop layer, the intermediate layer having an intermediate layer thickness; and

an etch layer of a third material disposed over the intermediate layer, the etch layer having an etch layer thickness,

wherein the intermediate layer thickness is such that a ratio of the etch layer thickness to the intermediate layer thickness is at most 3 times a first etch selectivity, wherein the first etch selectivity is the etching rate of the first material divided by an etching rate of the second material when exposed to a fluorocarbon etchant,

wherein the first and second materials are such that the first etch selectivity for the fluorocarbon etchant between the first and second materials is at least a ratio of 5;

1,

wherein the second and third materials are such that a second etch selectivity for a fluoro-methane etchant between the second and third materials is at least a ratio of 5;

1,

wherein the etch layer comprises an inclusion in a region to be etched for forming a via contact, and wherein the inclusion has an etching rate different than the etching rate of the third material when exposed to the fluorocarbon etchant.

17. The semiconductor structure of claim 16, wherein the metallic layer comprises aluminum, wherein the first material comprises titanium nitride, wherein the second material comprises silicon oxynitride, and wherein the third material comprises an oxide material.

18. The semiconductor structure of claim 16, wherein the etching rate of the inclusion is less than the etching rate of the third material when exposed to a fluorocarbon etchant.

19. The semiconductor structure of claim 16, wherein the inclusion is disposed under the intersecting sidewalls of the first and second non-uniformities.

20. The semiconductor structure of claim 16, wherein the etch layer has a minimum thickness at a bottom surface of the first non-uniformity.

21. The semiconductor structure of claim 16, wherein sidewalls of the first non-uniformity are non-uniform, and wherein a bottom surface of the first non-uniformity is non-uniform.

22. The semiconductor structure of claim 16, wherein a thickness of the intermediate layer is less than a product of the second etch selectivity and the stop layer thickness.

23. The semiconductor structure of claim 16, wherein the etching rate of the inclusion is greater than the etching rate of the third material when exposed to a fluorocarbon etchant.

24. The semiconductor structure of claim 23, wherein the inclusion comprises air.

25. The semiconductor structure of claim 16, wherein the etch layer comprises a first non-uniformity in a region to be etched for forming a via contact, and wherein the first non-uniformity extends substantially through the etch layer thickness.

26. The semiconductor structure of claim 25, further comprising a second non-uniformity in the region to be etched for forming the via contact, and wherein the second non-uniformity extends only partially through the etch layer thickness.

27. The semiconductor structure of claim 26, wherein a sidewall of the first non-uniformity intersects with a sidewall of the second non-uniformity.