System and method for ESD protection

• US 8,405,152 B2
• Filed: 10/07/2011
• Issued: 03/26/2013
• Est. Priority Date: 01/15/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Woo, Agnes N., Kindsfater, Kenneth R., Lu, Fang
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US13/268,386
• Publication Number:
  US 20120081822A1
• Time in Patent Office: 536 Days
• Field of Search: 257/355, 257/356, 257/357, 257/360
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H03D 1/22 Homodyne or synchrodyne circuits receiver circuits H04B1/30
• CPC Class Codes: H03G 1/0005 Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 2200/18 Tuning of a master filter in order to tune its slave filter
• CPC Class Codes: H03J 3/08 by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03K 17/164 using parallel switching arrangements
• CPC Class Codes: H03K 2217/96015 Constructional details for touch switches for capacitive touch switches see H03K2217/9607
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range.

Claims

1. An electrostatic discharge (ESD) protection system for an integrated circuit die, the integrated circuit die including a circuit core, the ESD protection system comprising:

a localized power supply bus disposed within the circuit core;

a localized ground bus disposed within the circuit core; and

an ESD clamp, coupled between the localized ground bus and the localized power supply bus, configured to provide a low impedance discharge path between the localized ground bus and the localized power supply bus.

2. The ESD protection system of claim 1, further comprising:

a plurality of bond pads configured to couple to the circuit core.

3. The ESD protection system of claim 2, further comprising:

a plurality of integrated circuit tracks configured to couple the plurality of bond pads to the circuit core.

4. The ESD protection system of claim 3, wherein the plurality of integrated circuit tracks is configured to bypass the localized power supply bus and the localized ground bus.

5. The ESD protection system of claim 2, wherein the plurality of bond pads is configured to couple to the localized power supply bus and the localized ground bus.

6. The ESD protection system of claim 2, further comprising:

a plurality of external connection tracks, configured to couple the plurality of bon pads to an external circuit.

7. The ESD protection system of claim 6, wherein the plurality of external connection tracks is configured to bypass the localized power supply bus and the localized ground bus.

8. The ESD protection system of claim 2, further comprising:

a ground ring disposed in an area between the plurality of bond pads and a periphery of the integrated circuit die; and

a power supply ring disposed in the area between the plurality of bond pads and the periphery of the integrated circuit die.

9. The ESD protection system of claim 8, further comprising:

a plurality of integrated circuit-tracks configured to bypass the ground ring and the power supply ring.

10. The ESD protection system of claim 8, further comprising:

a the plurality of connection tracks are configured to bypass the ground ring and the power supply ring.

11. The ESD protection system of claim 8, wherein the plurality of bond pads is configured to couple to the ground ring and the power supply ring.

12. An electrostatic discharge (ESD) protection system for an integrated circuit die, the integrated circuit die including a circuit core, the ESD protection system comprising:

a first set of bond pads disposed between the circuit core and a periphery of the integrated circuit die;

a second set of bond pads disposed within the circuit core;

a localized power supply bus disposed within the circuit core;

a localized ground bus disposed within the circuit core;

a ground ring disposed in an area between the first set of bond pads and the periphery of the integrated circuit die;

a first ESD clamp, coupled between the localized ground bus and the ground ring, configured to provide a low impedance discharge path between the localized ground bus and the ground ring; and

a second ESD clamp coupled between the localized ground bus and the localized power supply bus, configured to provide a low impedance discharge path between the localized ground bus and the localized power supply bus.

13. The ESD protection system of claim 12, further comprising:

a first set of integrated circuit tracks configured to couple the first set of bond pads to the circuit core; and

a second set of integrated circuit tracks configured to couple the second set of bond pads to the circuit core.

14. The ESD protection system of claim 13, further comprising:

a power supply ring disposed in an area between the first set of bond pads and the periphery of the integrated circuit die.

15. The ESD protection system of claim 14, wherein the first set and the second set of integrated circuit tracks are configured to bypass the ground ring, the power supply ring, the localized ground bus, and the localized power supply bus.

16. The ESD protection system of claim 14, wherein the first set of bond pads is configured to couple to the ground ring, the power supply ring, the local ground ring, and the local power supply ring.

18. The ESD protection system of claim 12, wherein the first set of bond pads and the second set of bond pads are configured to couple to an external circuit.

19. The ESD protection system of claim 18, further comprising:

a first set of external connection tracks configured to couple to the external circuit; and

a second set of external connection tracks configured to couple the second set of bond pads to the at least one external circuit.

20. The ESD protection system of claim 19, wherein the second set of external connection tracks is configured to bypass the power supply ring, the ground ring, the local power supply bus, and the localized ground bus.

17. The ESD protection system of 12, wherein the second set of bond pads is configured to couple to the localized ground bus and the localized power supply bus.