Tri-gate transistor device with stress incorporation layer and method of fabrication

• US 8,405,164 B2
• Filed: 04/26/2010
• Issued: 03/26/2013
• Est. Priority Date: 06/27/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hareland, Scott A., Chau, Robert S., Doyle, Brian S., Datta, Suman, Jin, Been-Yih
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US12/767,681
• Publication Number:
  US 20100200917A1
• Time in Patent Office: 1,065 Days
• Field of Search: 257/401, 257/618, 257/623, 257/E29.022
• US Class Current: 257/401
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

Claims

1. A semiconductor device comprising:

a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate;

a gate dielectric formed on said laterally opposite sidewalls of said semiconductor body;

a gate electrode formed over said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body; and

a silicon nitride film formed beneath said semiconductor body beneath said gate electrode wherein said silicon nitride film is formed over and around said gate electrode.

3. The device of claim 1 further comprising an oxide film disposed between said semiconductor body and said silicon nitride film beneath said gate electrode.

2. A semiconductor device comprising:

a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate;

a gate dielectric formed on said laterally opposite sidewalls of said semiconductor body;

a gate electrode formed over said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body;

a silicon nitride film formed beneath said semiconductor body beneath said gate electrode; and

a source region and a drain region formed in said semiconductor body on opposite sides of said gate electrode, wherein said silicon nitride film is formed around said source region and drain region in said semiconductor body.

4. A semiconductor device comprising:

a semiconductor material formed on a substrate, said semiconductor material forming semiconductor bodies and a source landing pad and a drain landing pad, said semiconductor bodies having a top surface and laterally opposite sidewalls, said semiconductor bodies electrically coupled together by said source landing pads and said drain landing pads;

a gate dielectric formed on said top surface and said laterally opposite sidewalls of said semiconductor bodies;

a gate electrode formed on said gate dielectric on said top surface and said laterally opposite sidewalls of said semiconductor bodies; and

a silicon nitride film formed beneath each of said semiconductor bodies; and

source and drain regions formed in said semiconductor bodies on opposite sides of said gate electrode and wherein said silicon nitride film is formed around said source and drain regions in said semiconductor bodies and on said source landing pad and said drain landing pad.

5. The device of claim 4 further comprising an oxide film formed between said semiconductor body and said silicon nitride film formed beneath said semiconductor body beneath said gate electrode.