Through-silicon via structure

• US 8,405,201 B2
• Filed: 07/15/2010
• Issued: 03/26/2013
• Est. Priority Date: 11/09/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yung-Chi, Wu, Weng-Jin, Shue, Shau-Lin
• Primary Examiner(s): Quach, Tuan N.
• Application Number:
  US12/836,720
• Publication Number:
  US 20110108986A1
• Time in Patent Office: 985 Days
• Field of Search: 257/698, 257/751, 257/761, 257/763, 257/764, 257/774, 257/E23.011, 438/667
• US Class Current: 257/698
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a block layer formed in a portion sandwiched between the metal layer and the metal seed layer. The block layer includes magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), cadmium (Cd), or combinations thereof.

Claims

1. An integrated circuit device, comprising:

a semiconductor substrate having a front surface and a back surface with an integrated circuit (IC) component formed on the front surface;

an interlayer dielectric (ILD) layer formed overlying the front surface of the semiconductor substrate;

a contact plug formed in the ILD layer and electrically connected to the IC component; and

a via structure formed in the ILD layer and extending through the semiconductor substrate, wherein the via structure comprises

a metal layer,

a metal seed layer surrounding the metal layer and having a sidewall,

a barrier layer surrounding the metal seed layer, and

a block layer sandwiched between the metal layer and the metal seed layer and extending along only a portion of the sidewall of the metal seed layer; and

wherein the block layer comprises at least one of magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), or cadmium (Cd).

2. The integrated circuit device of claim 1, wherein the metal seed layer comprises a bottom portion adjacent to the back surface of the semiconductor substrate, and the bottom portion of the metal seed layer is free of the block layer.

3. The integrated circuit device of claim 1, wherein the metal layer comprises copper, and the metal seed layer comprises copper.

4. The integrated circuit device of claim 1, wherein the barrier layer comprises at least one of TaN, Ta, TiN, or Ti.

5. The integrated circuit device of claim 1, wherein the via structure further comprises a passivation layer surrounding the barrier layer.

6. The integrated circuit device of claim 5, wherein the passivation layer comprises silicon oxide.

7. The integrated circuit device of claim 1, wherein the via structure includes an end that is exposed on the back surface of the semiconductor substrate.

8. The integrated circuit device of claim 1, further comprising a semiconductor component stacked on the back surface of the semiconductor substrate and electrically connected to the via structure.

9. A semiconductor device, comprising:

a semiconductor substrate having a front surface and a back surface with an integrated circuit (IC) component formed on the front surface;

an interlayer dielectric (ILD) layer formed overlying the front surface of the semiconductor substrate;

a contact plug formed in the ILD layer and electrically connected to the IC component; and

a via structure formed in the ILD layer and extending through the semiconductor substrate;

wherein the via structure comprises a copper layer, a copper seed layer surrounding the copper layer and having a sidewall, a barrier layer surrounding the copper seed layer, and a manganese (Mn) layer sandwiched between the copper layer and the copper seed layer and extending along only a portion of the sidewall of the copper seed layer; and

wherein the via structure comprises an end that is exposed on the back surface of the semiconductor substrate.

10. The semiconductor device of claim 9, wherein the barrier layer comprises at least one of TaN, Ta, TiN, or Ti.

11. The semiconductor device of claim 9, further comprising a passivation layer surrounding the barrier layer.

12. The semiconductor device of claim 11, wherein the passivation layer comprises silicon oxide.

13. The semiconductor device of claim 9, further comprising a backside dielectric layer formed overlying the back surface of the semiconductor substrate;

and an external contact formed on the backside dielectric layer.

14. The semiconductor device of claim 13, wherein the external contact comprises solder bumps, copper-containing bumps or combinations thereof.

15. An integrated circuit (IC) device, comprising:

a substrate having an opening defined therein, a front surface, a back surface, and an IC component formed on the front surface, the opening extending from the front surface of the substrate to the back surface;

an interconnection structure over the front surface of the substrate and electrically coupled to the IC component; and

a via structure in the opening, extending through the substrate, and electrically coupled to the interconnection structure, the via structure comprising;

a metal layer;

a metal seed layer surrounding the metal layer and having a sidewall;

a barrier layer surrounding the metal seed layer; and

a block layer sandwiched between the metal layer and the metal seed layer and extending along only a portion of the sidewall of the metal seed layer, the block layer comprises a material including manganese (Mn), magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), or cadmium (Cd).

16. The IC device of claim 15, wherein the via structure further comprises a passivation layer between the barrier layer and a sidewall of the opening.

17. The IC device of claim 16, wherein the passivation layer comprises silicon oxide.

18. The IC device of claim 15, wherein the metal seed layer comprises a bottom portion adjacent to the back surface of the substrate, and the block layer is between the front surface of the substrate and the bottom portion of the metal seed layer.

19. The IC device of claim 15, wherein the metal layer comprises copper, and the metal seed layer comprises copper.

20. The IC device of claim 15, wherein the barrier layer comprises TaN, Ta, TiN, or Ti.