Semiconductor package

• US 8,405,212 B2
• Filed: 06/18/2010
• Issued: 03/26/2013
• Est. Priority Date: 12/31/2009
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chu, Chi-Chih, Weng, Cheng-Yi
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Booker, Vicki B
• Application Number:
  US12/818,422
• Publication Number:
  US 20110156251A1
• Time in Patent Office: 1,012 Days
• Field of Search: 257/738, 257/E23.021
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 Diameter ranges

Abstract

The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least one opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads.

Claims

1. A semiconductor package, comprising:

a substrate, comprising a top surface, a pad and a solder mask, wherein the pad is disposed adjacent to the top surface of the substrate, and the solder mask overlies and directly contacts a part of the pad and defines a first opening so as to expose a remaining part of the pad;

at least one chip, mounted on the substrate;

a plurality of conductive elements, electrically connecting the chip and the substrate;

a conductor, disposed over the pad; and

a molding compound, disposed on the top surface of the substrate, wherein the molding compound defines a second opening so as to expose a remaining part of the conductor and a top end of the conductor is recessed below a top surface of the molding compound, and wherein the second opening has a side surface extending from the top surface of the molding compound to the conductor, and the side surface is curved.

2. The semiconductor package as claimed in claim 1, wherein the substrate further comprises a plating layer that is disposed on the remaining part of the pad exposed by the first opening of the solder mask.

3. The semiconductor package as claimed in claim 2, wherein a width of the plating layer is smaller than a width of the pad.

4. The semiconductor package as claimed in claim 2, wherein the plating layer comprises at least one of gold and nickel.

5. The semiconductor package as claimed in claim 1, wherein a bottom surface of the solder mask is substantially coplanar with a top surface of the pad.

6. The semiconductor package as claimed in claim 1, wherein a width of the second opening at the top surface of the molding compound is greater than a width of the conductor.

7. The semiconductor package as claimed in claim 1, wherein the pad comprises copper.

8. A semiconductor package, comprising:

a substrate comprising a top surface, a pad, and a solder mask, wherein a bottom surface of the solder mask is substantially coplanar with a top surface of the pad, and wherein the solder mask defines a first opening that partially exposes the pad to define a covered portion and an uncovered portion of the pad;

a conductor disposed over the uncovered portion of the pad; and

a molding compound disposed over the top surface of the substrate, wherein the molding compound comprises a top surface and defines a second opening that exposes a top end of the conductor, and the top end of the conductor is recessed below the top surface of the molding compound.

9. The semiconductor package as claimed in claim 8, wherein the solder mask directly contacts the covered portion of the pad.

10. The semiconductor package as claimed in claim 8, wherein the covered portion of the pad is adjacent to a periphery of the pad.

11. The semiconductor package as claimed in claim 8, wherein the conductor is solder.

12. The semiconductor package as claimed in claim 8, wherein the substrate further comprises an anti-oxidation layer disposed over the uncovered portion of the pad.

13. The semiconductor package as claimed in claim 12, wherein the anti-oxidation layer is inwardly recessed from a periphery of the pad.

14. The semiconductor package as claimed in claim 8, wherein a width of the first opening at a top surface of the solder mask is substantially the same as a width of the first opening adjacent to the pad.

15. A semiconductor package, comprising:

a substrate comprising a top surface, a pad, and a solder mask, wherein the pad is disposed adjacent to the top surface of the substrate, and the solder mask extends over a peripheral part of the pad while a central part of the pad is exposed;

a chip disposed over the top surface of the substrate;

a conductor disposed over the central part of the pad; and

a molding compound disposed over the top surface of the substrate, wherein the molding compound comprises a top surface and defines an opening that at least partially exposes the conductor, and a width of the opening at the top surface of the molding compound is at least as large as a width of the conductor.

16. The semiconductor package as claimed in claim 15, wherein the solder mask directly contacts the peripheral part of the pad.

17. The semiconductor package as claimed in claim 15, wherein the width of the opening at the top surface of the molding compound is greater than the width of the conductor.

18. The semiconductor package as claimed in claim 15, wherein a top end of the conductor is recessed below the top surface of the molding compound.

19. The semiconductor package as claimed in claim 15, wherein the substrate further comprises a plating layer extending over the central part of the pad but without extending over the peripheral part of the pad.

20. The semiconductor package as claimed in claim 15, wherein the opening has a side surface extending from the top surface of the molding compound to the conductor, and the side surface is curved.