Systems and methods for intelligently optimizing operating efficiency using variable gate drive voltage

• US 8,405,373 B2
• Filed: 12/30/2011
• Issued: 03/26/2013
• Est. Priority Date: 04/29/2009
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Tsai, Fu-Sheng, Mathew, Abey K.
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Finch, III, Fred E
• Application Number:
  US13/341,031
• Publication Number:
  US 20120098511A1
• Time in Patent Office: 452 Days
• Field of Search: 323/267, 323/272, 323/282, 323/283, 323/285, 363/21.05, 363/21.13
• US Class Current: 323/283
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel

Abstract

Systems and methods for intelligently optimizing voltage regulation efficiency for information handling systems by varying gate drive voltage value based on measured operating efficiency and/or other voltage regulation operating parameters. Different voltage regulation operating parameters may be dynamically monitored and recorded during a power conversion process, and these operating parameters may then be used to dynamically and variably control gate drive voltage level to improve/optimize voltage regulation operating efficiency performance.

Claims

1. A method for regulating voltage in an information handling system, comprising:

providing DC/DC voltage regulation circuitry coupled to supply power to a system load of said information handling system, said DC/DC voltage regulation circuitry including a power processing circuit comprising one or more drive transistors;

providing gate drive voltage controller circuitry, power monitoring controller circuitry, and gate drive voltage regulation circuitry;

using the gate drive voltage regulation circuitry to regulate power supplied by said DC/DC voltage regulation circuitry to said system load of said information handling system by driving the gate of said one or more drive transistors of said power processing circuit with two or more different gate drive voltage levels;

using the power monitoring controller circuitry to determine two or more real time operating efficiency values of said power processing circuit while said power processing circuit is driven at each of two or more respective gate drive voltage levels; and

using the gate drive voltage controller circuitry to vary the value of said gate drive voltage level provided by said gate drive voltage regulation circuitry to drive the gate of said one or more drive transistors of said power processing circuit, and using the gate drive voltage controller circuitry to determine whether the gate drive voltage is to be increased, decreased or left unchanged based on said determined two or more real time operating efficiency values of said power processing circuit;

where the gate drive voltage controller circuitry is separate from the power processing circuit, the power monitoring controller circuitry, and the gate drive voltage regulation circuitry; and

where the gate drive voltage controller circuitry comprises a microcontroller or processor.

2. The method of claim 1, further comprising:

(a) using the gate drive voltage regulation circuitry to regulate voltage supplied by said DC/DC voltage regulation circuitry to said system load of said information handling system by driving the gate of said one or more drive transistors of said power processing circuit with a first gate drive voltage level, and using the power monitoring controller circuitry to determine a first real time operating efficiency of said power processing circuit while said power processing circuit is driven with said first gate drive voltage level;

(b) using the gate drive voltage regulation circuitry to regulate voltage supplied by said DC/DC voltage regulation circuitry to said system load of said information handling system by driving the gate of said one or more drive transistors of said power processing circuit with a second gate drive voltage level that is greater than or less than said first gate drive voltage level, and using the power monitoring controller circuitry to determine a second real time operating efficiency of said power processing circuit while said power processing circuit is driven with said second gate drive voltage level;

(c) using the gate drive voltage controller circuitry to compare said first real time operating efficiency to said second real time operating efficiency;

(d) using the gate drive voltage controller circuitry to determine a third gate drive voltage level based on said comparison of said first real time operating efficiency to said second real time operating efficiency according to one of the following relationships;

determining said third gate drive voltage level to be greater than said second gate drive voltage level if said second gate drive voltage level is greater than said first gate drive voltage level and said second real time operating efficiency is greater than said first real time operating efficiency, or

determining said third gate drive voltage level to be less than said second gate drive voltage level if said second gate drive voltage level is greater than said first gate drive voltage level and said second real time operating efficiency is not greater than said first real time operating efficiency;

or

determining said third gate drive voltage level to be less than said second gate drive voltage level if said second gate drive voltage level is less than said first gate drive voltage level and said second real time operating efficiency is greater than said first real time operating efficiency;

or

determining said third gate drive voltage level to be greater than said second gate drive voltage level if said second gate drive voltage level is less than said first gate drive voltage level and said second real time operating efficiency is not greater than said first real time operating efficiency; and

(e) using the gate drive voltage regulation circuitry to regulate voltage supplied by said DC/DC voltage regulation circuitry to said system load of said information handling system by driving the gate of said one or more drive transistors of said power processing circuit with said determined third gate drive voltage level.

3. The method of claim 2, further comprising iteratively repeating said steps (a) through (e) for the duration of time that said DC/DC voltage regulation circuitry is supplying power to said system load of said information handling system;

wherein said first gate drive voltage level of step (a) of each subsequent iteration is equal to said third gate drive voltage level of step (e) of the immediately previous iteration.

4. The method of claim 2, wherein said step (d) further comprises using the gate drive voltage controller circuitry to determine said third gate drive voltage level based on said comparison of said first real time operating efficiency to said second real time operating efficiency according to one of the following relationships:

determining said third gate drive voltage level to be greater than said second gate drive voltage level if said second gate drive voltage level is greater than said first gate drive voltage level and said second real time operating efficiency is greater than said first real time operating efficiency by a predetermined amount, or

determining said third gate drive voltage level to be less than said second gate drive voltage level if said second gate drive voltage level is greater than said first gate drive voltage level and said second real time operating efficiency is not greater than said first real time operating efficiency by said predetermined amount;

or

determining said third gate drive voltage level to be less than said second gate drive voltage level if said second gate drive voltage level is less than said first gate drive voltage level and said second real time operating efficiency is greater than said first real time operating efficiency by said predetermined amount;

or

determining said third gate drive voltage level to be greater than said second gate drive voltage level if said second gate drive voltage level is less than said first gate drive voltage level and said second real time operating efficiency is not greater than said first real time operating efficiency by said predetermined amount.

5. The method of claim 1, further comprising using said drive voltage regulation circuitry to initially provide a pre-determined value of said gate drive voltage level upon power up of said information handling system.

6. The method of claim 1, further comprising using the gate drive voltage controller circuitry to determine a value of said first gate drive voltage level based on previous optimized values of said gate drive voltage level.

7. The method of claim 1, further comprising providing a digital communication bus to couple together said power processing circuit, said power monitoring controller circuitry, said gate drive voltage regulation circuitry, and said gate drive voltage controller circuitry, the digital communication bus comprising at least one of a system management bus (SMBus), power management bus (PMBus), or inter-integrated circuitry (I²C) bus;

providing said real time operating efficiency values to said gate drive voltage controller circuitry from said power monitoring controller circuitry across said digital communication bus; and

providing commands from said gate drive voltage controller to the gate drive voltage regulation circuitry across said digital communication bus to control said power processing circuit.

8. The method of claim 7, further comprising providing said real time operating efficiency values to said gate drive voltage controller circuitry from said power monitoring controller circuitry and providing commands from the gate drive voltage controller circuitry to the gate drive voltage regulation circuitry to control said power processing circuit all across the same common digital communication bus.

9. The method of claim 1, further comprising:

providing main voltage regulation circuitry that includes both said power processing circuit and said power monitoring controller circuitry together, the main voltage regulation circuitry being separate circuitry from the gate drive voltage controller circuitry;

providing a common digital communication bus that couples together the separate circuitries of the main voltage regulation circuitry, the main voltage regulation circuitry, and the gate drive voltage controller circuitry;

using the power monitoring controller circuitry of the main voltage regulation circuitry to gather real time operating parameter information;

using the power monitoring controller circuitry of the main voltage regulation circuitry to provide the gathered real time operating parameter information to the gate drive voltage controller circuitry across the common digital communication bus, the gathered real time operating parameter information including the real time operating efficiency of the main voltage regulation circuitry;

using the gate drive voltage controller circuitry to communicate a gate drive voltage command across the common digital communication bus to the gate drive voltage regulation circuitry to control the level of gate drive voltage provided by said gate drive voltage regulation circuitry based on the real time operating efficiency of the main voltage regulation circuitry.

10. The method of claim 9, where the gathered real time operating parameter information communicated across the common digital communication bus further includes real time input DC voltage (V_IN) to the DC/DC voltage regulation circuitry, real time input current (I_IN) to the DC/DC voltage regulation circuitry, real time output DC voltage (V_OUT) from the DC/DC voltage regulation circuitry, and real time output current (I_OUT) from the DC/DC voltage regulation circuitry;

and where each of real time operating efficiency, V_IN, V_OUT, I_IN, and I_OUT are all communicated in real time across the same common digital communication bus from the main voltage regulation circuitry to the gate drive voltage controller circuitry.

11. The method of claim 1, further comprising using the power monitoring controller circuitry to determine the duty cycle of the one or more drive transistors in order to regulate power to be supplied by said DC/DC voltage regulation circuitry to said system load of said information handling system.

12. DC/DC voltage regulation circuitry for an information handling system, comprising:

a power processing circuit configured to provide current of regulated output DC voltage to power a system load of an information handling system, said power processing circuit comprising one or more drive transistors;

power monitoring controller circuitry configured to determine real time operating efficiency values of said power processing circuit while said power processing circuit is driven at different gate drive voltage levels;

gate drive voltage regulation circuitry configured to provide gate drive voltage to drive the gate of said one or more drive transistors of said power processing circuit with two or more different gate drive voltage levels; and

gate drive voltage controller circuitry provided separate from the power processing circuit, the power monitoring controller circuitry, and the gate drive voltage regulation circuitry, the gate drive voltage controller circuitry being configured to control the level of gate drive voltage provided by said gate drive voltage regulation circuitry, the gate drive voltage controller circuitry being further configured to determine whether the gate drive voltage is to be increased, decreased or left unchanged based on said measured real time operating efficiency values of said power processing circuit;

where the gate drive voltage controller circuitry comprises a microcontroller or processor.

13. The DC/DC voltage regulation circuitry of claim 12, further comprising a digital communication bus that comprises at least one of a system management bus (SMBus), power management bus (PMBus), or inter-integrated circuitry (I²C) bus;

where said digital communication bus couples together said power processing circuit, said power monitoring controller circuitry, said gate drive voltage regulation circuitry, and said gate drive voltage controller circuitry;

wherein said power monitoring controller circuitry is configured to provide said real time operating efficiency values to said gate drive voltage controller circuitry across said digital communication bus; and

wherein said gate drive voltage controller circuitry is configured to provide commands to the gate drive voltage regulation circuitry across said digital communication bus to control said power processing circuit.

14. The DC/DC voltage regulation circuitry of claim 13, wherein said power monitoring controller circuitry is further configured to provide said real time operating efficiency values to said gate drive voltage controller circuitry across the same common digital communication bus across which said gate drive voltage controller circuitry provides commands to the gate drive voltage regulation circuitry to control said power processing circuit.

15. The DC/DC voltage regulation circuitry of claim 12, further comprising main voltage regulation circuitry coupled to said gate drive voltage regulation circuitry and said gate drive voltage controller circuitry by a digital communication bus that comprises at least one of a system management bus (SMBus), power management bus (PMBus), or inter-integrated circuitry (I²C) bus;

and wherein said main voltage regulation circuitry includes said power processing circuit and said power monitoring controller circuitry.

16. The DC/DC voltage regulation circuitry of claim 12, wherein said gate drive voltage regulation circuitry is configured to provide gate drive voltage to drive the gate of said one or more drive transistors of said power processing circuit with first and second different gate drive voltage levels, said second gate drive voltage level being greater than or less than said first gate drive voltage level;

wherein said power monitoring controller circuitry is configured to determine first and second real time operating efficiency values of said power processing circuit while said power processing circuit is driven with said respective first and second gate drive voltage levels;

wherein said gate drive voltage controller circuitry is configured to compare said first real time operating efficiency to said second real time operating efficiency and to determine a third gate drive voltage level based on said comparison according to one of the following relationships;

said third gate drive voltage level determined to be greater than said second gate drive voltage level if said second gate drive voltage level is greater than said first gate drive voltage level and said second operating efficiency is greater than said first operating efficiency, or

said third gate drive voltage level determined to be less than said second gate drive voltage level if said second gate drive voltage level is greater than said first gate drive voltage level and said second operating efficiency is not greater than said first operating efficiency;

or

said third gate drive voltage level determined to be less than said second gate drive voltage level if said second gate drive voltage level is less than said first gate drive voltage level and said second operating efficiency is greater than said first operating efficiency;

or

said third gate drive voltage level determined to be greater than said second gate drive voltage level if said second gate drive voltage level is less than said first gate drive voltage level and said second operating efficiency is not greater than said first operating efficiency; and

wherein said gate drive voltage controller circuitry is further configured to control said gate drive voltage regulation circuitry to drive the gate of said one or more drive transistors of said power processing circuit with said determined third gate drive voltage level.

17. The DC/DC voltage regulation circuitry of claim 16, wherein said DC/DC voltage regulation circuitry is configured to iteratively repeat providing said first and second different gate drive voltage levels;

wherein said power monitoring controller circuitry is configured to iteratively determine real time operating efficiency values of said power processing circuit while said power processing circuit is driven during each iteration with said first and second gate drive voltage levels;

wherein said gate drive voltage controller circuitry is configured to iteratively compare said first real time operating efficiency to said second real time operating efficiency of each iteration and to determine a third gate drive control voltage level for each iteration based on said comparison and according to one of said relationships; and

wherein said gate drive voltage controller is further configured to control said gate drive voltage regulation circuitry to drive the gate of said one or more drive transistors of said power processing circuit with said third gate drive voltage level determined each iteration.

18. The DC/DC voltage regulation circuitry of claim 12, wherein upon power up of said DC/DC voltage regulation circuitry, said gate drive voltage controller circuitry is configured to initially set said first gate drive voltage level to a pre-determined value.

19. The DC/DC voltage regulation circuitry of claim 12, wherein said gate drive voltage controller circuitry is configured to determine a value of said first gate drive voltage level based on previous optimized values of said gate drive voltage level.

20. The DC/DC voltage regulation circuitry of claim 12, where:

the main voltage regulation circuitry includes both said power processing circuit and said power monitoring controller circuitry together, the main voltage regulation circuitry being separate circuitry from the gate drive voltage controller circuitry;

the DC/DC voltage regulation circuitry further comprises a common digital communication bus that couples together the separate circuitries of the main voltage regulation circuitry, the main voltage regulation circuitry, and the gate drive voltage controller circuitry;

the power monitoring controller circuitry of the main voltage regulation circuitry is configured to gather real time operating parameter information, and to provide the gathered real time operating parameter information to the gate drive voltage controller circuitry across the common digital communication bus, the gathered real time operating parameter information including the real time operating efficiency of the main voltage regulation circuitry;

the gate drive voltage controller circuitry is configured to communicate a gate drive voltage command across the common digital communication bus to the gate drive voltage regulation circuitry to control the level of gate drive voltage provided by said gate drive voltage regulation circuitry based on the real time operating efficiency of the main voltage regulation circuitry.

21. The DC/DC voltage regulation circuitry of claim 20, where the gathered real time operating parameter information communicated across the common digital communication bus further includes real time input DC voltage (V_IN) to the DC/DC voltage regulation circuitry, real time input current (I_IN) to the DC/DC voltage regulation circuitry, real time output DC voltage (V_OUT) from the DC/DC voltage regulation circuitry, and real time output current (I_OUT) from the DC/DC voltage regulation circuitry;

and where the power monitoring controller circuitry of the main voltage regulation circuitry is further configured to communicate each of real time operating efficiency, V_IN, V_OUT, I_IN, and I_OUT all in real time across the same common digital communication bus from the main voltage regulation circuitry to the gate drive voltage controller circuitry.

22. The DC/DC voltage regulation circuitry of claim 12, where the power monitoring controller circuitry is configured to determine the duty cycle of the one or more drive transistors for regulating power to be supplied by said DC/DC voltage regulation circuitry to said system load of said information handling system.

23. The DC/DC voltage regulation circuitry of claim 12, where the provided gate drive voltage controller circuitry is not coupled or configured to measure any one of real time input DC voltage (V_IN) to the DC/DC voltage regulation circuitry, real time input current (I_IN) to the DC/DC voltage regulation circuitry, real time output DC voltage (V_OUT) from the DC/DC voltage regulation circuitry, or real time output current (I_OUT) from the DC/DC voltage regulation circuitry;

and where the provided gate drive voltage controller circuitry is not coupled or configured to determine duty cycle or the real time operating efficiency of the main voltage regulation circuitry.

24. An information handling system, comprising:

a system load; and

DC/DC voltage regulation circuitry comprising;

a power processing circuit coupled to provide current of regulated output DC voltage to power said system load, said power processing circuit comprising one or more drive transistors,

power monitoring controller circuitry configured to determine real time operating efficiency values of said power processing circuit while said power processing circuit is driven at different gate drive voltage levels,

gate drive voltage regulation circuitry configured to provide gate drive voltage to drive the gate of said one or more drive transistors of said power processing circuit with two or more different gate drive voltage levels,

gate drive voltage controller circuitry provided separate from the power processing circuit, the power monitoring controller circuitry, and the gate drive voltage regulation circuitry, the gate drive voltage controller circuitry being configured to control the level of gate drive voltage provided by said gate drive voltage regulation circuitry, the gate drive voltage controller circuitry being further configured to determine whether the gate drive voltage is to be increased, decreased or left unchanged based on said measured real time operating efficiency values of said power processing circuit, and

where the gate drive voltage controller circuitry comprises a microcontroller or processor.

25. The information handling system of claim 24, wherein said gate drive voltage regulation circuitry is configured to provide gate drive voltage to drive the gate of said one or more drive transistors of said power processing circuit with first and second different gate drive voltage levels, said second gate drive voltage level being greater than or less than said first gate drive voltage level;

wherein said power monitoring controller circuitry is configured to determine first and second real time operating efficiency values of said power processing circuit while said power processing circuit is driven with said respective first and second gate drive voltage levels;

wherein said gate drive voltage controller circuitry is configured to compare said first real time operating efficiency to said second real time operating efficiency and to determine a third gate drive voltage level based on said comparison according to one of the following relationships;

said third gate drive voltage level determined to be greater than said second gate drive voltage level if said second gate drive voltage level is greater than said first gate drive voltage level and said second operating efficiency is greater than said first operating efficiency, or

said third gate drive voltage level determined to be less than said second gate drive voltage level if said second gate drive voltage level is greater than said first gate drive voltage level and said second operating efficiency is not greater than said first operating efficiency;

or

said third gate drive voltage level determined to be less than said second gate drive voltage level if said second gate drive voltage level is less than said first gate drive voltage level and said second operating efficiency is greater than said first operating efficiency;

or

said third gate drive voltage level determined to be greater than said second gate drive voltage level if said second gate drive voltage level is less than said first gate drive voltage level and said second operating efficiency is not greater than said first operating efficiency; and

wherein said gate drive voltage controller circuitry is further configured to control said gate drive voltage regulation circuitry to drive the gate of said one or more drive transistors of said power processing circuit with said determined third gate drive voltage level.

26. The information handling system of claim 25, wherein said DC/DC voltage regulation circuitry is configured to iteratively repeat providing said first and second different gate drive voltage levels;

wherein said power monitoring controller circuitry is configured to iteratively determine real time operating efficiency values of said power processing circuit while said power processing circuit is driven during each iteration with said first and second gate drive voltage levels;

wherein said gate drive voltage controller circuitry is configured to iteratively compare said first real time operating efficiency to said second real time operating efficiency of each iteration and to determine a third gate drive control voltage level for each iteration based on said comparison and according to one of said relationships; and

wherein said gate drive voltage controller is further configured to control said gate drive voltage regulation circuitry to drive the gate of said one or more drive transistors of said power processing circuit with said third gate drive voltage level determined each iteration.

27. The information handling system of claim 24, wherein said gate drive voltage controller circuitry is configured to determine a value of said first gate drive voltage level based on previous optimized values of said gate drive voltage level.

28. The information handling system of claim 24, further comprising a digital communication bus that comprises at least one of a system management bus (SMBus), power management bus (PMBus), or inter-integrated circuitry (I²C) bus;

where said digital communication bus couples together said power processing circuit, said power monitoring controller circuitry, said gate drive voltage regulation circuitry, and said gate drive voltage controller circuitry;

wherein said power monitoring controller circuitry is configured to provide said real time operating efficiency values to said gate drive voltage controller circuitry across said digital communication bus; and

wherein said gate drive voltage controller circuitry is configured to provide commands to the gate drive voltage regulation circuitry across said digital communication bus to control said power processing circuit.

29. The information handling system of claim 24, further comprising main voltage regulation circuitry coupled to said gate drive voltage regulation circuitry and said gate drive voltage controller circuitry by a digital communication bus that comprises at least one of a system management bus (SMBus), power management bus (PMBus), or inter-integrated circuitry (I²C) bus;

and wherein said main voltage regulation circuitry includes said power processing circuit and said power monitoring controller circuitry.

30. A method for regulating voltage in an information handling system, comprising:

providing DC/DC voltage regulation circuitry coupled to supply power to a system load of said information handling system, said DC/DC voltage regulation circuitry including a power processing circuit comprising one or more drive transistors;

providing gate drive voltage controller circuitry, power monitoring controller circuitry, and gate drive voltage regulation circuitry;

using the gate drive voltage regulation circuitry to regulate power supplied by said DC/DC voltage regulation circuitry to said system load of said information handling system by driving the gate of said one or more drive transistors of said power processing circuit with two or more different gate drive voltage levels;

using the power monitoring controller circuitry to determine two or more real time operating efficiency values of said power processing circuit while said power processing circuit is driven at each of two or more respective gate drive voltage levels; and

using the gate drive voltage controller circuitry to vary the value of said gate drive voltage level provided by said gate drive voltage regulation circuitry to drive the gate of said one or more drive transistors of said power processing circuit based on a comparison of said determined two or more real time operating efficiency values of said power processing circuit;

where the gate drive voltage controller circuitry is separate from the power processing circuit, the power monitoring controller circuitry, and the gate drive voltage regulation circuitry;

where the gate drive voltage controller circuitry comprises a microcontroller or processor; and

where the method further comprises;

providing a digital communication bus to couple together said power processing circuit, said power monitoring controller circuitry, said gate drive voltage regulation circuitry, and said gate drive voltage controller circuitry, the digital communication bus comprising at least one of a system management bus (SMBus), power management bus (PMBus), or inter-integrated circuitry (I²C) bus, and

providing said real time operating efficiency values to said gate drive voltage controller circuitry from said power monitoring controller circuitry across said digital communication bus; and

providing commands from said gate drive voltage controller to the gate drive voltage regulation circuitry across said digital communication bus to control said power processing circuit.

31. DC/DC voltage regulation circuitry for an information handling system, comprising:

a power processing circuit configured to provide current of regulated output DC voltage to power a system load of an information handling system, said power processing circuit comprising one or more drive transistors;

power monitoring controller circuitry configured to determine the regulated output DC voltage (VOUT) of the power to be supplied by said DC/DC voltage regulation circuitry to said system load of said information handling system, and to determine real time operating efficiency values of said power processing circuit while said power processing circuit is driven at different gate drive voltage levels;

gate drive voltage regulation circuitry configured to provide gate drive voltage to drive the gate of said one or more drive transistors of said power processing circuit with two or more different gate drive voltage levels; and

gate drive voltage controller circuitry provided separate from the power processing circuit, the power monitoring controller circuitry, and the gate drive voltage regulation circuitry, the gate drive voltage controller circuitry being configured to control the level of gate drive voltage provided by said gate drive voltage regulation circuitry based on said measured real time operating efficiency values of said power processing circuit;

where the gate drive voltage controller circuitry comprises a microcontroller or processor;

where the DC/DC voltage regulation circuitry further comprises a digital communication bus that comprises at least one of a system management bus (SMBus), power management bus (PMBus), or inter-integrated circuitry (I₂C) bus;

where said digital communication bus couples together said power processing circuit, said power monitoring controller circuitry, said gate drive voltage regulation circuitry, and said gate drive voltage controller circuitry;

wherein said power monitoring controller circuitry is configured to provide said real time operating efficiency values to said gate drive voltage controller circuitry across said digital communication bus; and

wherein said gate drive voltage controller circuitry is configured to provide commands to the gate drive voltage regulation circuitry across said digital communication bus to control said power processing circuit.

32. An information handling system, comprising:

a system load; and

DC/DC voltage regulation circuitry comprising;

a power processing circuit coupled to provide current of regulated output DC voltage to power said system load, said power processing circuit comprising one or more drive transistors,

power monitoring controller circuitry configured to determine the regulated output DC voltage (VOUT) of the power to be supplied by said DC/DC voltage regulation circuitry to said system load, and to determine real time operating efficiency values of said power processing circuit while said power processing circuit is driven at different gate drive voltage levels,

gate drive voltage regulation circuitry configured to provide gate drive voltage to drive the gate of said one or more drive transistors of said power processing circuit with two or more different gate drive voltage levels,

gate drive voltage controller circuitry provided separate from the power processing circuit, the power monitoring controller circuitry, and the gate drive voltage regulation circuitry, the gate drive voltage controller circuitry being configured to control the level of gate drive voltage provided by said gate drive voltage regulation circuitry based on said measured real time operating efficiency values of said power processing circuit, and

where the gate drive voltage controller circuitry comprises a microcontroller or processor;

where the information handling system further comprises a digital communication bus that comprises at least one of a system management bus (SMBus), power management bus (PMBus), or inter-integrated circuitry (I²C) bus;

where said digital communication bus couples together said power processing circuit, said power monitoring controller circuitry, said gate drive voltage regulation circuitry, and said gate drive voltage controller circuitry;

wherein said power monitoring controller circuitry is configured to provide said real time operating efficiency values to said gate drive voltage controller circuitry across said digital communication bus; and

wherein said gate drive voltage controller circuitry is configured to provide commands to the gate drive voltage regulation circuitry across said digital communication bus to control said power processing circuit.

33. A method for regulating voltage in an information handling system, comprising:

providing DC/DC voltage regulation circuitry coupled to supply power to a system load of said information handling system, said DC/DC voltage regulation circuitry including a power processing circuit comprising one or more drive transistors;

providing gate drive voltage controller circuitry, power monitoring controller circuitry, and gate drive voltage regulation circuitry;

using the gate drive voltage regulation circuitry to regulate power supplied by said DC/DC voltage regulation circuitry to said system load of said information handling system by driving the gate of said one or more drive transistors of said power processing circuit with two or more different gate drive voltage levels;

using the power monitoring controller circuitry to determine two or more real time operating efficiency values of said power processing circuit while said power processing circuit is driven at each of two or more respective gate drive voltage levels; and

using the gate drive voltage controller circuitry to vary the value of said gate drive voltage level provided by said gate drive voltage regulation circuitry to drive the gate of said one or more drive transistors of said power processing circuit based on a comparison of said determined two or more real time operating efficiency values of said power processing circuit;

where the gate drive voltage controller circuitry is separate from the power processing circuit, the power monitoring controller circuitry, and the gate drive voltage regulation circuitry; and

where the gate drive voltage controller circuitry comprises a microcontroller or processor;

where the method further comprises;

(a) using the gate drive voltage regulation circuitry to regulate voltage supplied by said DC/DC voltage regulation circuitry to said system load of said information handling system by driving the gate of said one or more drive transistors of said power processing circuit with a first gate drive voltage level, and using the power monitoring controller circuitry to determine a first real time operating efficiency of said power processing circuit while said power processing circuit is driven with said first gate drive voltage level,

(b) using the gate drive voltage regulation circuitry to regulate voltage supplied by said DC/DC voltage regulation circuitry to said system load of said information handling system by driving the gate of said one or more drive transistors of said power processing circuit with a second gate drive voltage level that is greater than or less than said first gate drive voltage level, and using the power monitoring controller circuitry to determine a second real time operating efficiency of said power processing circuit while said power processing circuit is driven with said second gate drive voltage level,

(c) using the gate drive voltage controller circuitry to compare said first real time operating efficiency to said second real time operating efficiency,

(d) using the gate drive voltage controller circuitry to determine a third gate drive voltage level based on said comparison of said first real time operating efficiency to said second real time operating efficiency according to one of the following relationships;

determining said third gate drive voltage level to be greater than said second gate drive voltage level if said second gate drive voltage level is greater than said first gate drive voltage level and said second real time operating efficiency is greater than said first real time operating efficiency, or

determining said third gate drive voltage level to be less than said second gate drive voltage level if said second gate drive voltage level is greater than said first gate drive voltage level and said second real time operating efficiency is not greater than said first real time operating efficiency;

or

determining said third gate drive voltage level to be less than said second gate drive voltage level if said second gate drive voltage level is less than said first gate drive voltage level and said second real time operating efficiency is greater than said first real time operating efficiency;

or

determining said third gate drive voltage level to be greater than said second gate drive voltage level if said second gate drive voltage level is less than said first gate drive voltage level and said second real time operating efficiency is not greater than said first real time operating efficiency; and

(e) using the gate drive voltage regulation circuitry to regulate voltage supplied by said DC/DC voltage regulation circuitry to said system load of said information handling system by driving the gate of said one or more drive transistors of said power processing circuit with said determined third gate drive voltage level; and

wherein said step (d) further comprises using the gate drive voltage controller circuitry to determine said third gate drive voltage level based on said comparison of said first real time operating efficiency to said second real time operating efficiency according to one of the following relationships;

determining said third gate drive voltage level to be greater than said second gate drive voltage level if said second gate drive voltage level is greater than said first gate drive voltage level and said second real time operating efficiency is greater than said first real time operating efficiency by a predetermined amount, or

determining said third gate drive voltage level to be less than said second gate drive voltage level if said second gate drive voltage level is greater than said first gate drive voltage level and said second real time operating efficiency is not greater than said first real time operating efficiency by said predetermined amount;

or

determining said third gate drive voltage level to be less than said second gate drive voltage level if said second gate drive voltage level is less than said first gate drive voltage level and said second real time operating efficiency is greater than said first real time operating efficiency by said predetermined amount;

or

determining said third gate drive voltage level to be greater than said second gate drive voltage level if said second gate drive voltage level is less than said first gate drive voltage level and said second real time operating efficiency is not greater than said first real time operating efficiency by said predetermined amount.