System comprising a semiconductor device and structure

• US 8,405,420 B2
• Filed: 08/19/2010
• Issued: 03/26/2013
• Est. Priority Date: 04/14/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian, Beinglass, Israel, de Jong, J. L., Sekar, Deepak C.
• Primary Examiner(s): TRAN, THIENVU V
• Application Number:
  US12/859,665
• Publication Number:
  US 20110049577A1
• Time in Patent Office: 950 Days
• Field of Search: 326 37- 41, 326/47, 326101-102
• US Class Current: 326/41
• CPC Class Codes: G03F 9/7076 Mark details, e.g. phase grating mark, temporary mark
• CPC Class Codes: G03F 9/7084 Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Claims

1. A mobile device comprising a semiconductor device, the semiconductor device comprising:

a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying said first single crystal silicon layer, wherein said first alignment marks are detectable by a lithography tool to locate the lithography tool with respect to the first single crystal silicon layer; and

a second single crystal silicon layer overlying said at least one metal layer;

wherein said second single crystal silicon layer comprises a plurality of second transistors and second alignment marks, wherein said second alignment marks are detectable by the lithography tool to locate the lithography tool with respect to the second single crystal silicon layer,

wherein said second transistors are defined and aligned to said first transistors based on said first alignment marks and said second alignment marks.

2. A mobile device according to claim 1, wherein said second single crystal silicon layer is less than 0.4 micron thick.

3. A mobile device according to claim 1, wherein said second transistors are planar transistors.

4. A mobile device according to claim 1, wherein said second transistors comprise junction-less transistors.

5. A mobile device according to claim 1, wherein said second transistors comprise Recessed Channel Array Transistors (RCAT).

6. A mobile device according to claim 1, wherein said second single crystal silicon layer further comprises through vias through said second single crystal silicon layer,

wherein said through vias are aligned in a first direction to said first alignment marks and aligned in a second direction to said second alignment marks.

7. A mobile device according to claim 1, wherein said second transistors are gate-last transistors.

8. A system comprising a semiconductor device, the semiconductor device comprising:

a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials, wherein said first alignment marks are detectable by a lithography tool to locate the lithography tool with respect to the first single crystal silicon layer; and

a second single crystal silicon layer overlying said at least one metal layer;

wherein said second single crystal silicon layer comprises a plurality of second transistors comprising P type transistors and N type transistors;

wherein at least one of said second transistors is defined and aligned to said first alignment marks.

9. A system according to claim 8, wherein said second single crystal silicon layer is less than 0.4 micron thick.

10. A system according to claim 8, wherein said second transistors are planar transistors.

11. A system according to claim 8, wherein said second transistors comprise Recessed Channel Array Transistors (RCATs).

12. A system according to claim 8, wherein said second transistors comprise junction-less transistors.

13. A system according to claim 8,

wherein said second single crystal silicon layer comprises second alignment marks and through vias through said second single crystal silicon layer, wherein said second alignment marks are detectable by a lithography tool to locate the lithography tool with respect to the second single crystal silicon layer, and

wherein said through vias are aligned in a first direction to said first alignment marks and in a second direction to said second alignment marks.

14. A system according to claim 8, wherein said second transistors are gate-last transistors.