System and method for integrated timing control for an LCD display panel

• US 8,405,785 B1
• Filed: 08/25/2009
• Issued: 03/26/2013
• Est. Priority Date: 09/12/2008
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Inventors: Auld, David, He, Lei, Chen, Chen, Yeh, Gerard Kuang-Chang
• Primary Examiner(s): HAROLD, JEFFEREY F
• Assistant Examiner(s): Haiem, Sean
• Application Number:
  US12/547,143
• Time in Patent Office: 1,309 Days
• Field of Search: None
• US Class Current: 348/790
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers

Abstract

A television display system including a display system controller, a transmitter, and an integrated timing controller. The display system controller receives pixel data and pixel timing and control data, and responsive to a pixel data format corresponding to a selected communication standard of a plurality of communication standards that includes LVDS and at least one of RSDS and mini-LVDS, provides formatted pixel data formatted according to the pixel data format of the selected communication standard. The transmitter receives the formatted pixel data, and transmits the formatted pixel data for receipt according to a pixel data rate corresponding to the selected communication standard. The integrated timing controller receives the pixel timing and control data, and responsive to the selected communication standard being one of RSDS and mini-LVDS, generates pixel display timing and control signals to display the formatted pixel data at the pixel data rate corresponding to the selected communication standard on a television display.

Claims

1. A television display system comprising:

a display system controller configured to receive pixel data and pixel timing and control signals, and responsive to a pixel data format corresponding to a selected communication standard of a plurality of differential signaling communication standards that includes LVDS and at least one of RSDS and mini-LVDS, to provide formatted pixel data that is formatted according to the pixel data format of said selected communication standard;

a data framer configured to format the pixel data along with the pixel timing and control signals according to the pixel data format of LVDS responsive to LVDS being said selected communication standard, the data framer being configured to receive the pixel data and the pixel timing and control signals and to format only the pixel data according to the pixel data format of RSDS and mini-LVDS responsive to the selected one of RSDS and mini-LVDS being said selected communication standard;

a transmitter configured to receive the formatted pixel data, and to transmit the formatted pixel data for receipt according to a pixel data rate corresponding to said selected communication standard; and

an integrated timing controller configured to receive the pixel timing and control data, and responsive to said selected communication standard being one of RSDS and mini-LVDS, to generate pixel display timing and control signals to display the formatted pixel data at the pixel data rate corresponding to said selected communication standard on a television display;

wherein the data framer is further configured to format the pixel data at the pixel data rate of LVDS responsive to any one of LVDS, RSDS, and mini-LVDS being said selected communication standard, and to repeat each bit of the pixel data during formatting of the pixel data according to the pixel data format of RSDS and mini-LVDS responsive to the selected one of RSDS and mini-LVDS being said selected communication standard to provide an effective pixel data rate that is received according to the pixel data rate of the selected one of RSDS and mini-LVDS.

2. The television display system of claim 1, wherein the display system controller, the transmitter, and the integrated timing controller are implemented on a single integrated circuit.

3. The television display system of claim 2, wherein the plurality of differential signaling communication standards includes LVDS, RSDS, and mini-LVDS.

4. The television display system of claim 3, wherein the transmitter includes a plurality of drivers, the plurality of drivers including a first plurality of channel drivers configured to transmit the formatted pixel data for receipt according to the pixel data rate of LVDS responsive to LVDS being said selected communication standard, the first plurality of channel drivers being instead configured to transmit the formatted pixel data for receipt according to the pixel data rate of RSDS and mini-LVDS responsive to one of RSDS and mini-LVDS being said selected communication standard.

5. The television display system of claim 4, wherein the plurality of drivers includes at least one clock driver, the at least one clock driver being configured to transmit a clock signal having a clock rate that is one seventh the pixel data rate of LVDS responsive to any one of LVDS, RSDS and mini-LVDS being said selected communication standard.

6. The television display system of claim 4, wherein the plurality of drivers includes at least one clock driver, the at least one clock driver being configured to transmit a clock signal having a clock rate that is one eighth the pixel data rate of LVDS responsive to any one of LVDS, RSDS and mini-LVDS being said selected communication standard.

7. The television display system of claim 1, wherein the transmitter further includes a plurality of parallel to serial converters, each of the plurality of parallel to serial converters being coupled to a respective channel driver of the first plurality of channel drivers, each respective channel driver being configured to receive the formatted pixel data in a parallel data format and to convert the formatted pixel data to a serial data format at a rate that is eight times the data rate of LVDS responsive to any one of LVDS, RSDS, and mini-LVDS being said selected communication standard.

8. The television display system of claim 7, wherein the integrated timing controller includes:

a counter circuit to receive the pixel timing and control signals and to provide a line count signal and a pixel count signal, the line count signal identifying a line of the television display at which the formatted pixel data is to be displayed and the pixel count signal identifying pixel position of the television display at which the formatted pixel data is to be displayed; and

a plurality of programmable timing control circuits, coupled to the counter circuit each to receive the line count signal and the pixel count signal, the plurality of programmable timing control circuits including a first plurality of programmable timing control circuits for respectively providing a respective one of a plurality of source driver timing and control signals to the television display based upon the line count signal and the pixel count signal, and a second plurality of programmable timing control circuits for respectively providing a respective one of a plurality of gate driver timing and control signals to the television display based upon the line count signal and the pixel count signal.

9. The television display system of claim 8, wherein an assertion level, an assertion time, and an assertion width of each respective one of the plurality of source driver timing and control signals and each respective one of the plurality of gate driver timing and control signals is programmable.

10. The television display system of claim 9, wherein each of the plurality of programmable timing control circuits receives a programmable line start value, a programmable line end value, a programmable pixel start value, and a programmable pixel end value, the programmable line start value identifying a first line of the television display at which a first control signal is to be asserted, the programmable line end value identifying a last line of the television display at which the first control signal is to be deasserted, the programmable pixel start value identifying a first pixel position of the television display at which a second control signal is to be asserted, and the programmable pixel end value identifying a last pixel position of the television display at which the second control signal is to be deasserted, and wherein an output of each respective programmable timing control circuit is a selective Boolean combination of the first and second control signals.

11. The television display system of claim 1, wherein the transmitter includes a plurality of drivers, the plurality of drivers including a first plurality of channel drivers configured to transmit the formatted pixel data for receipt according to the pixel data rate of LVDS responsive to LVDS being said selected communication standard, the first plurality of channel drivers being instead configured to transmit the formatted pixel data for receipt according to the pixel data rate of RSDS and mini-LVDS responsive to one of RSDS and mini-LVDS being said selected communication standard.

12. The television display system of claim 1, wherein the transmitter includes at least one clock driver, the at least one clock driver being configured to transmit a clock signal having a clock rate that is one seventh the pixel data rate of LVDS responsive to any one of LVDS, RSDS and mini-LVDS being said selected communication standard.

13. The television display system of claim 1, wherein the transmitter includes at least one clock driver, the at least one clock driver being configured to transmit a clock signal having a clock rate that is one eighth the pixel data rate of LVDS responsive to any one of LVDS, RSDS and mini-LVDS being said selected communication standard.

14. The television display system of claim 1, wherein the integrated timing controller includes:

a counter circuit to receive the pixel timing and control signals and to provide a line count signal and a pixel count signal, the line count signal identifying a line of the television display at which the formatted pixel data is to be displayed and the pixel count signal identifying pixel position of the television display at which the formatted pixel data is to be displayed; and

a plurality of programmable timing control circuits, coupled to the counter circuit each to receive the line count signal and the pixel count signal, the plurality of programmable timing control circuits including a first plurality of programmable timing control circuits for respectively providing a respective one of a plurality of source driver timing and control signals to the television display based upon the line count signal and the pixel count signal, and a second plurality of programmable timing control circuits for respectively providing a respective one of a plurality of gate driver timing and control signals to the television display based upon the line count signal and the pixel count signal.

15. A method of displaying an image comprising acts of:

receiving pixel data and pixel timing and control signals corresponding to the image;

formatting, responsive to selection of LVDS from a plurality of differential signaling communication standards that includes LVDS and a least one of RSDS and mini-LVDS, the pixel data along with the pixel timing and control signals according to the pixel data format of said selected communication standard; and

;

formatting, responsive to selection of one of RSDS and mini-LVDS from the plurality of differential signaling communication standards, only the pixel data according to the pixel data format of said selected communication standard;

transmitting the formatted pixel data for receipt according to a pixel data rate corresponding said selected communication standard; and

generating, responsive to said selected communication standard being one of RSDS and mini-LVDS, pixel display timing and control signals to display the formatted pixel data at the pixel data rate corresponding to said selected communication standard on a television display;

wherein each of the acts of formatting includes formatting the pixel data for transmission at the pixel data rate of LVDS, and wherein the act of formatting only the pixel data includes repeating each bit of the pixel data a plurality of times during the act of formatting only the pixel data to provide an effective pixel data rate that is received according to the pixel data rate of RSDS and mini-LVDS.

16. The method of claim 15, wherein the act of formatting includes an act of:

formatting, responsive to selection of the communication standard from a plurality of differential signaling communication standards that includes LVDS, RSDS, and mini-LVDS, the pixel data according to a pixel data format of said selected communication standard.

17. The method of claim 16, wherein the act of transmitting includes acts of:

transmitting the formatted pixel data for receipt according to the pixel data rate of LVDS in response to LVDS being said selected communication standard; and

transmitting the formatted pixel data for receipt according to the pixel data rate of RSDS and mini-LVDS in response to one of RSDS and mini-LVDS being said selected communication standard.

18. The method of claim 17, wherein the act of transmitting the formatted pixel data for receipt according to the pixel data rate of LVDS in response to LVDS being said selected communication standard includes transmitting a first portion of the formatted pixel data for receipt according to the pixel data rate of LVDS using a first channel driver, and wherein the act of transmitting the formatted pixel data for receipt according to the pixel data rate of RSDS and mini-LVDS in response to one of RSDS and mini-LVDS being said selected communication standard includes transmitting a second portion of the formatted pixel data for receipt according to the pixel data rate of RSDS and mini-LVDS using the first channel driver.

19. The method of claim 18, further comprising an act of:

transmitting a clock signal having a clock rate that is one seventh the pixel data rate of LVDS in response to any one of LVDS, RSDS and mini-LVDS being said selected communication standard.

20. The method of claim 18, further comprising an act of:

transmitting a clock signal having a clock rate that is one eighth the pixel data rate of LVDS in response to any one of LVDS, RSDS and mini-LVDS being said selected communication standard.

21. The method of claim 15, further comprising an act of:

converting the formatted pixel data in a parallel data format to a serial data format at a rate that is eight times the pixel data rate of LVDS responsive to any one of LVDS, RSDS, and mini-LVDS being said selected communication standard.

22. The method of claim 21, further comprising an act of:

receiving a plurality of parameters corresponding to a viewable area of the television display;

wherein the act of generating includes an act of generating, responsive to said selected communication standard being one of RSDS and mini-LVDS, the pixel display timing and control signals to display the formatted pixel data at the pixel data rate corresponding to said selected communication standard on a television display based upon the plurality of parameters corresponding to the viewable area of the television display.