Pixel structure of a display panel

• US 8,405,787 B2
• Filed: 03/17/2009
• Issued: 03/26/2013
• Est. Priority Date: 09/05/2008
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Liu, Sheng-Chao, Lin, Hsiang-Lin, Liu, Kuang-Hsiang, Lin, Ching-Huan, Lin, Ming-Tien
• Primary Examiner(s): Le, Uyen Chau N
• Assistant Examiner(s): CHU, CHRIS H
• Application Number:
  US12/405,247
• Publication Number:
  US 20100059758A1
• Time in Patent Office: 1,470 Days
• Field of Search: 349/38, 349/39
• US Class Current: 349/39
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

A tri-gate pixel structure includes three sub-pixel regions, three gate lines, a data line, three thin film transistors (TFTs), three pixel electrodes, and a common line. The gate lines are disposed along a first direction, and the data line is disposed along a second direction. The TFTs are disposed in the sub-pixel regions respectively, wherein each TFT has a gate electrode electrically connected to a corresponding gate line, a source electrode electrically connected to the data line, and a drain electrode. The three pixel electrodes are disposed in the three sub-pixel regions respectively, and each pixel electrode is electrically connected to the drain electrode of one TFT respectively. The common line crosses the gate lines and partially overlaps the three gate lines, and the common line and the three pixel electrodes are partially overlapped to respectively form three storage capacitors.

Claims

1. A tri-gate pixel structure formed on a substrate, the substrate comprising three sub-pixel regions, the tri-gate pixel structure comprising:

three gate lines disposed along a first direction on the substrate;

a data line disposed along a second direction on the substrate;

three thin film transistors disposed on each of the sub-pixel regions respectively, each of the thin film transistors comprising a gate electrode, a source electrode and a drain electrode, wherein the gate electrode of each of the thin film transistors is electrically connected to the corresponding gate line, and the source electrode of each of the thin film transistors is electrically connected to the data line;

three pixel electrodes disposed in each of the sub-pixel regions respectively, and electrically connected to the corresponding drain electrode of each of the thin film transistors respectively; and

a common line disposed on the substrate, wherein the common line crosses the gate lines, partially overlaps with the gate lines, and the common line and the pixel electrodes partially overlap, forming three storage capacitors, respectively;

wherein the common line comprises a first common section disposed along the second direction and a plurality of second common extension parts coupled to the first common section to form three closed patterns substantially surrounding the three sub-pixel regions, and the common line and the data line are made of a same conductive layer.

2. The tri-gate pixel structure of claim 1, wherein the common line and the gate lines are made of different conductive layers.

3. The tri-gate pixel structure of claim 1, wherein each of the sub-pixel regions comprises a rectangular region, and a long axis of the rectangular region is disposed along the first direction.

4. The tri-gate pixel structure of claim 1, wherein the second common extension part and the gate line partially are overlapped, and the second common extension part comprises an opening pattern partially exposing the gate line.

5. The tri-gate pixel structure of claim 1, wherein at least a part of the common line is disposed on the same surface with the source electrode, the drain electrode, or the data line.

6. The tri-gate pixel structure of claim 1, wherein the common line does not overlap the data line.

7. The tri-gate pixel structure of claim 1, wherein the common line and the data line are simultaneously formed by the same conductive layer.

8. A liquid crystal display panel, comprising:

a first substrate comprising a plurality of pixel region, each pixel region comprising three sub-pixel regions, each pixel region comprising a pixel structure, the pixel structure comprising;

three gate lines disposed along a first direction on the first substrate;

a data line disposed along a second direction on the first substrate;

three thin film transistors disposed on each of the sub-pixel regions respectively, each of the thin film transistors comprising a gate electrode, a source electrode and a drain electrode, wherein the gate electrode of each of the thin film transistors is electrically connected to the corresponding gate line, and the source electrode of each of the thin film transistors is electrically connected to the data line;

three pixel electrodes disposed in each of the sub-pixel regions respectively, and electrically connected to the corresponding drain electrode of each of the thin film transistors respectively; and

a common line disposed on the first substrate, wherein the common line crosses the gate lines, partially overlaps with the gate lines, and the common line and the pixel electrodes partially overlap, forming three storage capacitors, respectively;

wherein the common line comprises a first common section disposed along the second direction and a plurality of second common extension parts coupled to the first common section to form three closed patterns substantially surrounding the three sub-pixel regions, and the common line and the data line are made of a same conductive layer;

a second substrate disposed opposite to the first substrate; and

a liquid crystal layer interposed between the first substrate and the second substrate.

9. The liquid crystal display panel of claim 8, wherein the second common extension part and the gate line partially are overlapped, and the second common extension part comprises an opening pattern partially exposing the gate line.

10. A pixel structure of a display panel formed on a substrate, the substrate comprising a plurality of sub-pixel regions, the pixel structure comprising:

a gate line disposed along a first direction on the substrate;

a data line disposed along a second direction on the substrate;

a thin film transistor disposed in the sub-pixel region, the thin film transistor comprising a gate electrode, a source electrode and a drain electrode, wherein the gate electrode of the thin film transistor is electrically connected to the gate line, and the source electrode of the thin film transistor is electrically connected to the data line;

a pixel electrode disposed in the sub-pixel region and electrically connected to the drain electrode of the thin film transistor; and

a common line disposed on the substrate and partially overlapping with the gate line, wherein the common line and the pixel electrode partially overlap, forming a storage capacitor, wherein the common line comprises a first common section disposed along the second direction and at least a second common extension part coupled to the first common section to form a closed pattern substantially surrounding the sub-pixel region, and the common line and the data line are made of a same conductive layer.

11. The pixel structure of the display panel of claim 10, wherein the common line and the gate line are made of different conductive layers.

12. The pixel structure of the display panel of claim 10, wherein the second common extension part and the gate line partially are overlapped, and the second common extension part comprises an opening pattern partially exposing the gate line.