Spread spectrum clock generating circuit

• US 8,406,271 B2
• Filed: 08/20/2010
• Issued: 03/26/2013
• Est. Priority Date: 08/27/2009
• Status: Expired due to Fees

• Current Assignee: IPGoal Microelectronics (Sichuan) Co., Ltd.
• Original Assignee: IPGoal Microelectronics (Sichuan) Co., Ltd.
• Inventors: Wu, Guosheng, Zhang, Ziche
• Primary Examiner(s): Kim, Kevin
• Application Number:
  US12/860,685
• Publication Number:
  US 20110051779A1
• Time in Patent Office: 949 Days
• Field of Search: 375/130, 375/140, 375/373, 375/376, 375/377, 327/291, 327/156
• US Class Current: 375/130
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

A spread spectrum generating circuit comprises an external PLL and an internal PLL. The external PLL comprises a phase detector, a low-pass filter, a voltage-controlled oscillator and a frequency divider, each of them connecting successively. The frequency divider is connected to the phase detector in order to form an external loop. The internal PLL comprises the phase detector, the low-pass filter and the voltage-controlled oscillator of the external PLL, each of them connecting successively. An output terminal of the voltage-controlled oscillator connects with a counter, and the output terminal of the counter connects to an input of the oscillator in order to form an internal loop. The present invention is compatible with the conventional ones, and has lower design risk and higher circuit reliability; compared with the general circuit, it has drastically reduced the area and power consumption, which allows more flexible design and meets more demands.

Claims

1. A spread spectrum clock generating circuit, comprising:

an external PLL (phase-locked loop); and

an internal PLL,

wherein the external PLL comprises a phase detector, a low-pass filter, a voltage-controlled oscillator and a frequency divider, each of them connecting successively, wherein the frequency divider is connected to the phase detector in order to form an external loop;

the internal PLL comprises the phase detector, the low-pass filter and the voltage-controlled oscillator of the external PLL, each of them connecting successively, wherein an output terminal of the voltage-controlled oscillator is connected with a counter, and an output terminal of the counter is connected to an input terminal of the oscillator in order to form an internal loop,

wherein a direct outputting clock of the voltage-controlled oscillator outputs a spread spectrum clock through an output buffer;

the outputted spread spectrum clock is also sent to the counter;

after counting M clock cycles, the counter outputs a pulse signal and sends the pulse signal into the input terminal of the voltage-controlled oscillator so as to form the internal loop,

wherein M is a natural number selected randomly.

2. The spread spectrum clock generating circuit, as recited in claim 1, wherein the phase detector has two input clock signals, one is a reference clock and the other one is a feedback clock, and two output signals which respectively correspond in phase to the two input signals;

the two outputted signals are further outputted to the low-pass filter;

the low-pass filter outputs level signals into the voltage-controlled oscillator and then the oscillator outputs the spread spectrum clock;

after having been divided by the frequency divider, the spread spectrum clock generates the feedback clock, and then the feedback clock is outputted through an output of the frequency divider to an input terminal of the phase detector in order to form the external phase-locked loop.

3. A spread spectrum clock generating circuit, comprising:

an external PLL (phase-locked loop); and

an internal PLL,

wherein the external PLL comprises a phase detector, a low-pass filter, a voltage-controlled oscillator and a frequency divider, each of them connecting successively, wherein the frequency divider is connected to the phase detector in order to form an external loop;

the internal PLL comprises the phase detector, the low-pass filter and the voltage-controlled oscillator of the external PLL, each of them connecting successively, wherein an output terminal of the voltage-controlled oscillator is connected with a counter, and an output terminal of the counter is connected to an input terminal of the oscillator in order to form an internal loop,

wherein when working normally, once the external PLL gets into a locked status, the voltage-controlled oscillator controls and keeps a constant voltage, and then outputs a spread spectrum clock into the counter;

after counting M clock cycles, the counter outputs a pulse signal and simultaneously gets cleared.

4. The spread spectrum clock generating circuit, as recited in claim 3, wherein the pulse signal will change periodically one of three electric characteristics in order to change periodically a frequency of a direct outputting clock of the voltage-controlled oscillator—

currents of a current source of an output drive of the voltage-controlled oscillator, currents of a current sink of the output drive of the voltage-controlled oscillator, and a load capacity of a load network of the voltage-controlled oscillator.

5. The spread spectrum clock generating circuit, as recited in claim 4, wherein the three electric characteristics have a following process to change the frequency of the direct outputting clock:

the bigger the currents of the current source of the output drive of the voltage-controlled oscillator are, the shorter a rise time of the direct outputting clock is;

meanwhile, a fall time of the direct outputting clock is not going to change, so the shorter a total cycle is, the bigger the frequency is;

contrarily, the less the currents of the current source are, the shorter the fall time of the direct outputting clock is;

since the rise time is not going to change, the longer the total cycle is, and the less the frequency is;

the bigger the currents of the current sink of the output drive of the voltage-controlled oscillator are, the shorter the fall time of the direct outputting clock is;

meanwhile, since the rise time of the direct outputting clock is not going to change, the shorter the total cycle is, the bigger the frequency is;

contrarily, the less the currents of the current sink, the shorter the rise time;

also, because of the unchanging fall time, the longer the total cycle, the less the frequency;

the less the load capacity of the load network of the voltage-controlled oscillator, the shorter the rise time of the direct outputting clock, meanwhile, the fall time gets shorter, accordingly the shorter the total cycle, the bigger the frequency;

contrarily, the more the load capacity of the load network, the shorter the fall time of the direct outputting clock;

meanwhile, the rise time gets shorter, so the longer the total cycle gets, the less the frequency gets.