Dynamic SLC/MLC blocks allocations for non-volatile memory

• US 8,407,400 B2
• Filed: 11/12/2008
• Issued: 03/26/2013
• Est. Priority Date: 11/12/2008
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Marotta, Giulio, De Santis, Luca, Vali, Tommaso
• Primary Examiner(s): PEUGH, BRIAN R
• Application Number:
  US12/269,766
• Publication Number:
  US 20100122016A1
• Time in Patent Office: 1,595 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode.

Claims

1. An apparatus comprising:

a flash memory having a number of memory blocks, wherein one or more of the memory blocks can operate in at least two modes of operation, the at least two modes of operation differing in a number of states to which a cell of a respective one of the blocks can be programmed and/or erased; and

a controller configured to operate the one or more of the memory blocks in one of the two modes of operation based at least partly on at least one of an amount of the memory in use or available for use, wherein the controller is configured to operate cells of at least one of the blocks in a mode of operation wherein the cells are programmed and/or erased to one of two states when the amount of the memory in use is less than a threshold.

2. The apparatus of claim 1, wherein the controller is further configured to operate cells of at least one of the blocks in a different mode of operation wherein the cells are programmed and/or erased to one of two states when the amount of the memory in use is greater than or equal to a threshold.

3. The apparatus of claim 1, wherein the controller is configured to relax data existing in the memory when the amount of the memory in use becomes less than a threshold.

4. The apparatus of claim 1, wherein the controller is configured to program available data bits into a block of single-level cells or a block of multi-level cells.

5. The apparatus of claim 1, wherein the flash memory comprises a NAND flash memory array.

6. The apparatus of claim 5, wherein the NAND flash memory array is on a chip or card.

7. The apparatus of claim 1, wherein the controller is configured to operate the one or more of the memory blocks in one of the two modes of operation based only on the amount of the memory in use.

8. The apparatus of claim 1, wherein the controller is configured to operate the one or more of the memory blocks in one of the two modes of operation based on the amount of the memory in use and available for use.

9. An apparatus comprising:

a flash memory having a number of memory blocks, wherein one or more of the memory blocks can operate in at least two modes of operation, the at least two modes of operation differing in a number of states to which a cell of a respective one of the blocks can be programmed and/or erased; and

a controller configured to operate the one or more of the memory blocks in one of the two modes of operation based at least partly on at least one of an amount of the memory in use or available for use, wherein the controller is configured to operate cells of at least one of the blocks in a mode of operation wherein the cells are programmed and/or erased to one of two states when the amount of the memory in use is greater than or equal to a threshold, wherein the threshold is about half of a capacity of the memory.

10. The apparatus of claim 9, wherein the controller is configured to program available data bits into a block of single-level cells or a block of multi-level cells.

11. The apparatus of claim 9, wherein the flash memory comprises a NAND flash memory array.

12. The apparatus of claim 9, wherein the controller is configured to operate the one or more of the memory blocks in one of the two modes of operation based only on the amount of the memory in use.

13. The apparatus of claim 9, wherein the controller is configured to operate the one or more of the memory blocks in one of the two modes of operation based on the amount of the memory in use and available for use.

14. The apparatus of claim 9, wherein the controller is configured to relax data existing in the memory when the amount of the memory in use becomes less than a threshold.

15. An apparatus comprising:

a flash memory having a number of memory blocks, wherein one or more of the memory blocks can operate in at least two modes of operation, the at least two modes of operation differing in a number of states to which a cell of a respective one of the blocks can be programmed and/or erased; and

a controller configured to operate the one or more of the memory blocks in one of the two modes of operation based at least partly on at least one of an amount of the memory in use or available for use, wherein the controller is configured to compact data existing in the memory when the amount of the memory in use nears a threshold.

16. The apparatus of claim 15, wherein the controller is configured to relax data existing in the memory when the amount of the memory in use becomes less than a threshold.

17. The apparatus of claim 15, wherein the controller is configured to program available data bits into a block of single-level cells or a block of multi-level cells.

18. The apparatus of claim 15, wherein the flash memory comprises a NAND flash memory array.

19. The apparatus of claim 15, wherein the controller is configured to operate the one or more of the memory blocks in one of the two modes of operation based only on the amount of the memory in use.

20. The apparatus of claim 15, wherein the controller is configured to operate the one or more of the memory blocks in one of the two modes of operation based on the amount of the memory in use and available for use.

21. A method of allocating memory blocks within a flash memory, the method comprising:

receiving data to be programmed in the flash memory;

responsive to receiving the data, dynamically allocating a block of memory cells as a block of single-level cells or a block of multi-level cells based at least partly on at least one of an amount of the memory already in use or an amount of the memory available for use; and

programming the data into the allocated block.

22. The method of claim 21, wherein the data received comprises data that is not allocated as a block of single-level cells or a block of multi-level cells.

23. The method of claim 21, wherein data received comprises data that is allocated as a block of single-level cells or a block of multi-level cells.

24. The method of claim 21, further comprising allocating the block of memory cells as a block of multi-level cells when the memory already in use is greater or equal to a threshold.

25. The method of claim 21, wherein the controller is configured to operate the allocated block as a block of single level cells or as a block of multilevel cells based only on the amount of the memory in use.

26. The method of claim 21, wherein the controller is configured to operate the allocated block as a block of single level cells or as a block of multilevel cells based only on the amount of the memory available for use.

27. The method of claim 21, wherein the controller is configured to operate the allocated block as a block of single level cells or as a block of multilevel cells based on the amount of the memory in use and available for use.

28. A method of allocating memory blocks within a flash memory, the method comprising:

receiving data to be programmed in the flash memory;

dynamically allocating a block of memory cells as a block of single-level cells or a block of multi-level cells based at least partly on at least one of an amount of the memory already in use or an amount of the memory available for use;

programming the data into the allocated block; and

setting a threshold amount of the memory in use above a user'"'"'s average memory use.

29. A method of allocating memory blocks within a flash memory, the method comprising:

receiving data to be programmed in the flash memory;

dynamically allocating a block of memory cells as a block of single-level cells or a block of multi-level cells based at least partly on at least one of an amount of the memory already in use or an amount of the memory available for use;

programming the data into the allocated block; and

setting a different threshold amount for the memory to switch operating from a first mode to a second mode than for the memory to switch operating from the second mode to the first mode.

30. A method of allocating memory blocks within a flash memory, the method comprising:

receiving data to be programmed in the flash memory;

dynamically allocating a block of memory cells as a block of single-level cells or a block of multi-level cells based at least partly on at least one of an amount of the memory already in use or an amount of the memory available for use;

programming the data into the allocated block; and

allocating the block of memory cells as a block of single-level cells when the memory already in use is less than a threshold.