Obscuring memory access patterns in conjunction with deadlock detection or avoidance

• US 8,407,425 B2
• Filed: 12/28/2007
• Issued: 03/26/2013
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gueron, Shay, Sheaffer, Gad, Raikin, Shlomo
• Primary Examiner(s): Rutz, Jared
• Assistant Examiner(s): SIMONETTI, NICHOLAS J
• Application Number:
  US11/966,794
• Publication Number:
  US 20090172304A1
• Time in Patent Office: 1,915 Days
• Field of Search: 710 48- 50, 710200-244, 711/141, 711146-147, 711150-152, 711/154, 711/156, 711/163, 714/39, 714/47, 714/704
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 21/556 involving covert channels, i.e. data leakage between processes inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]

Abstract

Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.

Claims

1. A computer-implemented method, comprising:

executing, via a first thread, one or more instructions to register a handler module to be invoked in response to an access, via a second thread, to one or more specified memory locations;

transferring control from the first thread to the handler module in response to data being evicted, via the access by the second thread, from one or more of the specified memory locations;

recording, in a register, an address of a second instruction of the first thread that was executing at the time of control transfer to the handler module;

incrementing an address-specific counter in response to each control transfer to the handler module such that the address-specific counter represents a number of times the handler module was invoked from the recorded address while the second instruction was executing; and

executing a deadlock policy responsive to the address-specific counter exceeding a maximum acceptable value, the deadlock policy affecting the first thread in response to execution.

2. The method of claim 1, wherein:

the address-specific counter is one of a plurality of address-specific counters, each address-specific counter being associated with a different instruction of the first thread.

3. The method of claim 1, wherein:

executing the deadlock policy further comprises aborting execution of the first thread.

4. The method of claim 1, wherein:

executing the deadlock policy further comprises presenting a message to a user.

5. The method of claim 1, further comprising:

returning control from the handler to the first thread.

6. The method of claim 5, further comprising:

loading data to the specified one or more memory locations before returning control to the first thread.

7. An article comprising:

a non-transitory storage medium having a plurality of machine accessible instructions;

wherein, when the instructions are executed by a processor, the instructions provide for;

executing, via a first thread, one or more instructions to register a handler module to be invoked in response to an access, via a second thread, to one or more specified memory locations;

transferring control from the first thread to the handler module in response to data being evicted, via the access by the second thread, from one or more of the specified memory locations;

recording an address of an instruction of the first thread that was executing at the time of control transfer to the handler module;

incrementing an address-specific counter in response to each control transfer to the handler module such that the address-specific counter represents a number of times the handler module was invoked from the recorded address while the associated instruction of the first thread was executing; and

executing a deadlock policy responsive to the address-specific counter exceeding a maximum acceptable value, the deadlock policy affecting the first thread in response to execution.

8. The article of claim 7, wherein:

the address-specific counter is one of a plurality of address-specific counters, each address-specific counter being associated with a different instruction of the first thread; and

said instructions further provide that the address-specific counter is incremented responsive to determining that the handler module has been invoked from the instruction of the first thread.

9. The article of claim 7, wherein the instructions that provide for executing the deadlock policy further provide for, when executed by the processor:

comprises aborting execution of the first thread.

10. The article of claim 7, wherein the instructions that provide for executing the deadlock policy further provide for, when executed by the processor:

presenting a message to a user.

11. The article of claim 7, wherein the instructions further provide for, when executed by a processor:

returning control from the handler to the first thread.

12. The article of claim 11, wherein the instructions that provide for returning control from the handler to the first thread further comprise, when executed by the processor:

loading data to the specified one or more memory locations before returning control to the first thread.

13. A system, comprising:

a memory resource coupled to a first thread unit and a second thread unit;

the first thread unit including in its instruction set architecture an instruction to monitor a specified location of the memory resource;

wherein the instruction set architecture of the first thread unit further includes an instruction to register a handler module to be invoked in response to modification of data at said specified location by the second thread unit; and

wherein the memory resource is further to store code that includes instructions to (i) increment an address-specific counter each time the handler module is invoked such that the address-specific counter represents a number of times control was transferred from the first thread unit to the handler module while the first thread unit was executing an instruction at an address indicated by the address-specific counter and (ii) execute a deadlock policy, in response to the address-specific counter having a predetermined relationship with a maximum value, the deadlock policy affecting the first thread unit in response to execution.