Non-volatile semiconductor memory storing an inverse map for rebuilding a translation table
First Claim
1. A non-volatile semiconductor memory comprising:
- a non-volatile memory array including a plurality of blocks, each block comprising a plurality of memory segments each assigned a physical address; and
control circuitry operable to;
read a logical address from an inverse map stored in the non-volatile memory array, wherein the logical address corresponds to a physical address of one of the memory segments;
when the memory segment corresponding to the logical address is valid, update a translation table using the logical address, wherein the translation table maps logical addresses to physical addresses;
when the memory segment corresponding to the logical address is invalid, update a dirty table using the physical address of the memory segment; and
use the dirty table to perform a garbage collection operation, wherein invalid memory segments are erased without being relocated.
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Accused Products
Abstract
A non-volatile semiconductor memory is disclosed comprising a non-volatile memory array including a plurality of blocks, each block comprising a plurality of memory segments each assigned a physical address. A logical address is read from a first block, wherein the logical address corresponds to a physical address of one of the memory segments. When the memory segment corresponding to the logical address is valid, a translation table is updated using the logical address, wherein the translation table for mapping logical addresses to physical addresses. When the memory segment corresponding to the logical address is invalid, a dirty table is updated using the logical address. The dirty table is used to perform a garbage collection operation, wherein invalid memory segments are erased without being relocated.
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Citations
22 Claims
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1. A non-volatile semiconductor memory comprising:
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a non-volatile memory array including a plurality of blocks, each block comprising a plurality of memory segments each assigned a physical address; and control circuitry operable to; read a logical address from an inverse map stored in the non-volatile memory array, wherein the logical address corresponds to a physical address of one of the memory segments; when the memory segment corresponding to the logical address is valid, update a translation table using the logical address, wherein the translation table maps logical addresses to physical addresses; when the memory segment corresponding to the logical address is invalid, update a dirty table using the physical address of the memory segment; and use the dirty table to perform a garbage collection operation, wherein invalid memory segments are erased without being relocated. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of operating a non-volatile semiconductor memory comprising a non-volatile memory array including a plurality of blocks, each block comprising a plurality of memory segments each assigned a physical address, the method comprising:
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reading a logical address from an inverse map stored in the non-volatile memory array, wherein the logical address corresponds to a physical address of one of the memory segments; when the memory segment corresponding to the logical address is valid, updating a translation table using the logical address, wherein the translation table maps logical addresses to physical addresses; when the memory segment corresponding to the logical address is invalid, updating a dirty table using the physical address of the memory segment; and using the dirty table to perform a garbage collection operation, wherein invalid memory segments are erased without being relocated. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method of operating a non-volatile semiconductor memory comprising (1) a non-volatile memory array including a plurality of blocks, each block comprising a plurality of memory segments each assigned a physical address and (2) a volatile memory, the method comprising:
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upon a power-up of the non-volatile semiconductor memory, generating, in the volatile memory, a translation table for mapping logical addresses to physical addresses in the non-volatile memory array, the generating comprising; reading at least one entry comprising a logical address from an inverse map stored in the non-volatile memory array, wherein the logical address corresponds to a physical address of one of the memory segments, and wherein entries in the inverse map correspond to a chronological write order of the memory segments in the non-volatile memory array; in response to determining that the memory segment corresponding to the logical address is valid, updating the translation table using the logical address when the memory segment corresponding to the logical address is invalid, updating a dirty table using the physical address of the memory segment; and using the dirty table to perform a garbage collection operation, wherein invalid memory segments are erased without being relocated.
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22. A non-volatile semiconductor memory comprising:
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a non-volatile memory array including a plurality of blocks, each block comprising a plurality of memory segments each assigned a physical address; a volatile memory; and control circuitry operable to; upon a power-up of the non-volatile semiconductor memory, generate, in the volatile memory, a translation table for mapping logical addresses to physical addresses in the non-volatile memory array, the control circuitry operable to generate by at least; reading at least one entry comprising a logical address from an inverse map stored in the non-volatile memory array, wherein the logical address corresponds to a physical address of one of the memory segments, and wherein entries in the inverse map correspond to a chronological write order of the memory segments in the non-volatile memory array; in response to determining that the memory segment corresponding to the logical address is valid, updating the translation table using the logical address when the memory segment corresponding to the logical address is invalid, update a dirty table using the physical address of the memory segment; and use the dirty table to perform a garbage collection operation, wherein invalid memory segments are erased without being relocated.
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Specification