Method and apparatus for generating jitter test patterns on a high performance serial bus

• US 8,407,535 B2
• Filed: 06/05/2006
• Issued: 03/26/2013
• Est. Priority Date: 04/21/2000
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Whitby-Strevens, Colin
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US11/422,301
• Publication Number:
  US 20060209943A1
• Time in Patent Office: 2,486 Days
• Field of Search: None
• US Class Current: 714/704
• CPC Class Codes: H04B 17/0085 using test signal generators
• CPC Class Codes: H04L 1/244 test sequence generators

Abstract

The present invention provides a method for generating random jitter test patterns by generating a sequence of maximum-size asynchronous packets according to the P1394b standard and transmitting the sequence to the device under test. The present invention provides a method for generating jitter test patterns by disabling the transmitter data scrambler of the second device; clearing the port_error register of the device under test; and sending a test pattern to said device under test. The present invention provides for a method for generating supply noise test patterns comprising: transmitting a test pattern to the DUT comprising a maximum length asynchronous packet containing alternate 0016 and FF16 bytes.

Claims

1. A method of performing a jitter test in a communications system, said communications system comprising a device under test operatively coupled to a second device, the method comprising:

generating a test pattern, said test pattern comprising an asynchronous packet addressed to an unused node number;

transmitting said asynchronous packet to said device under test, the transmission causing the device under test to recover a clock by analyzing the timing of one or more data edges of the test pattern;

repeating said act of transmitting at least once; and

wherein an error rate due to jitter in said communications system is computed by regularly reading a port error register.

2. The method of claim 1, wherein said test pattern contains alternate 00₁₆ and FF₁₆ bytes.

3. The method of claim 1, wherein said act of generating is performed by said second device.

4. The method of claim 3, wherein said second device comprises a transmitter data scrambler, and said transmitter data scrambler may operate in either an enabled state or a disabled state.

5. The method of claim 4, wherein said transmitter data scrambler is in said enabled state during said act of transmitting.

6. The method of claim 5, wherein said transmitter data scrambler is in said enabled state during said act of repeating.

7. The method of claim 1, wherein:

said device under test comprises a plurality of ports; and

said jitter test tests each of said plurality of ports independently.

8. The method of claim 1, wherein:

said act of transmitting is performed on a port of said second device; and

said port of said second device is capable of operating at a maximum operating speed of a port on said device under test.

9. The method of claim 8, wherein said device under test comprises a plurality of ports, and said jitter test tests each of said plurality of ports independently.

10. The method of claim 9, wherein said communications system comprises an IEEE 1394b compliant system.

11. A device for transmitting a jitter test pattern over a communications bus to a device under test, said device comprising:

a processing apparatus;

a port capable of transmitting said jitter test pattern over said communications bus when said port is operatively coupled to said device under test;

a transmit scrambler operatively coupled to said port; and

a computer readable medium comprising one or more computer executable instructions that, when executed by said processing apparatus;

generate a first jitter test pattern, said first jitter test pattern comprising an asynchronous packet having a length which is equal to a maximum allowed value for said communications bus, and comprising a normal header, a checksum, and a packet payload of all zero values;

scramble said first jitter test pattern using said transmit scrambler;

transmit said asynchronous packet to said device under test; and

repeat said act of transmitting at least once, ignoring a fairness protocol on the port.

12. The device of claim 11, wherein said transmit scrambler may operate in either an enabled state or a disabled state.

13. The device of claim 11, wherein said device under test comprises a plurality of ports, and said computer executable instructions comprise one or more instructions that tests each of said plurality of ports of said device under test independently.

14. The device of claim 11, wherein said port is capable of operating at a maximum operating speed of a port on said device under test.

15. The device of claim 11, wherein said communications bus comprises a bus compliant with IEEE 1394b.

16. A method of testing a device under test in a communications system, said device under test being in data communication with a second device, the method comprising:

generating a test pattern, said test pattern comprising at least 42 null packets followed by a packet containing at least 50 bytes of consecutive D21.5 symbols;

disabling a scrambler once synchronization is achieved between said device under test and said second device;

transmitting said test pattern to said device under test; and

analyzing said transmitted asynchronous packets to determine an effect of jitter in said communications system.

17. The method of claim 16, wherein said test pattern comprises a random pattern that is transmitted continuously.

18. The method of claim 16, wherein said communications system is compliant with the IEEE 1394b standard.

19. The method of claim 18, wherein transmitting said at least 42 null packets comprises repeatedly issuing CURRENT_ASYNC requests.

20. The method of claim 18, wherein said transmission is accomplished at least in part by ignoring fairness.

21. The method of claim 16, further comprising:

capturing each transmitted packet; and

examining said captured packet to determine the effects of jitter on the transmitted asynchronous packet.

22. The method of claim 21, wherein said act of capturing is performed by a time interval analyzer (TIA).

26. The method of claim 16, wherein said at least 42 null packets are generated by repeatedly issuing CURRENT_ASYNC requests and providing a zero-length PHY packet.

27. The method of claim 16, wherein said 42 null packets are generated through generating at least one quadlet PHY packet containing a D30.3 symbol.

23. A device for transmitting a jitter test pattern over a communications bus to a device under test, said device comprising:

an IEEE 1394b compliant system;

a processing apparatus;

a port capable of transmitting said jitter test pattern over said communications bus when said port is operatively coupled to said device under test, the transmission causing the device under test to recover a clock by analyzing the timing of one or more data edges of the test pattern;

a transmit scrambler operatively coupled to said port; and

a computer readable medium comprising one or more computer executable instructions that are configured to, when executed by said processing apparatus;

generate a first jitter test pattern, said first jitter test pattern comprising a maximum length asynchronous packet;

transmit said maximum length asynchronous packet to said device under test in a scrambled or form based on the operation of the scrambler; and

repeat said act of transmitting at least once.

24. The device of claim 23, wherein said jitter test pattern contains alternate 00₁₆ and FF₁₆ bytes.

25. The device of claim 23, further comprising:

a system bus electrically coupled to said port, the system bus configured to alternately communicate all ones and all zeros on successive clocks;

wherein said one or more computer executable instructions are configured to, when executed by said processing apparatus, transmit data across said system bus.