Error recover within processing stages of an integrated circuit

• US 8,407,537 B2
• Filed: 10/13/2010
• Issued: 03/26/2013
• Est. Priority Date: 03/20/2003
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.), Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Arm Limited (SoftBank Group Corp.), Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Flautner, Krisztian, Austin, Todd Michael, Blaauw, David Theodore, Mudge, Trevor Nigel
• Primary Examiner(s): Baker, Stephen M
• Application Number:
  US12/923,908
• Publication Number:
  US 20110126051A1
• Time in Patent Office: 895 Days
• Field of Search: 714/708, 714/745, 714/814, 714/819, 713/300, 713/503
• US Class Current: 714/708
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/104 using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check
• CPC Class Codes: G06F 11/1608 Error detection by comparing the output signals of redundant hardware G06F11/1629, G06F11/1666 take precedence; error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18; checking static stores for correct operation G11C29/00; for logic circuits H03K19/003, H03K19/007; for pulse counters or frequency dividers H03K21/40
• CPC Class Codes: G06F 11/167 Error detection by comparing the memory output
• CPC Class Codes: G06F 11/1695 which are operating with time diversity
• CPC Class Codes: G06F 11/183 by voting, the voting not being performed by the redundant components

Abstract

An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

Claims

1. An integrated circuit for performing data processing, said integrated circuit comprising:

an error detector configured to detect errors in operation of said integrated circuit;

error-repair circuitry configured to repair errors in operation of said integrated circuit; and

an operational parameter controller configured to control one or more performance controlling operational parameters of said integrated circuit;

wherein

said operational parameter controller controls at least one of said one or more performance controlling parameters in dependence upon one or more characteristics of errors detected by said error detector such that a gain in one or more performance characteristics of said integrated circuit from operating with said one or more performance controlling parameters having values resulting in errors in operation of said integrated circuit exceeds a loss in said one or more performance characteristics from repairing errors in operation of said integrated circuit with said error-repair circuitry.

2. An integrated circuit as claimed in claim 1, wherein said operational parameter controller applies feedback control to adjust said at least one of said one or more performance controlling parameters in dependence upon said one or more characteristics of errors detected by said error detector.

3. An integrated circuit as claimed in claim 1, wherein said one or more characteristics of errors detected by said error detector comprise at least one of:

an error rate of said errors detected by said error detector; and

a reduction in computational throughput resulting from repair by said error-repair logic of said errors detected by said error detector.

4. An integrated circuit as claimed in claim 1, wherein said one or more performance controlling parameters include at least one of:

an operating voltage;

an operating frequency;

an integrated circuit body bias voltage; and

temperature.

5. An integrated circuit as claimed in claim 1, wherein said one or more performance characteristics comprise one or more of:

computational throughput, energy consumption and power.

6. An integrated circuit as claimed in claim 1, wherein said error detector detects errors by double-sampling data signal values within said integrated circuit, a difference between sampled values being indicative of an error.

7. An integrated circuit as claimed in claim 6, wherein said double-sampling is detecting a signal value at a sampling point at respective different times.

8. An integrated circuit as claimed in claim 1 comprising:

a plurality of processing stages, a processing stage output signal from at least one processing stage being supplied as a processing stage input signal to a following processing stage, wherein said at least one processing stage comprises;

processing logic configured to perform a processing operation upon at least one processing stage input value to generate a processing logic output signal;

a non-delayed latch configured to capture a non-delayed value of said processing logic output signal at a non-delayed capture time, said non-delayed value being supplied to said following processing stage as said processing stage output signal following said non-delayed capture time; and

a delayed latch configured to capture a delayed value of said processing logic output signal at a delayed capture time later than said non-delayed capture time;

wherein said error detector comprises a comparator operable to compare said non-delayed value and said delayed value to detect a change in said processing logic output signal following said non-delayed capture time indicative of said processing logic not having finished said processing operation at said non-delayed capture time; and

said error-repair logic is configured when said comparator detects said change to perform an error-repair operation suppressing use of said non-delayed value by said following processing stage.

9. An integrated circuit as claimed in claim 8, comprising a meta-stability detector operable to detect meta-stability in said non-delayed value and trigger said error-repair logic to suppress use of said non-delayed value if found to be meta-stable.

10. An integrated circuit as claimed in claim 8, wherein when said comparator detects said change said error-repair logic is operable to force said delayed value to be stored in said non-delayed latch in place of said non-delayed value.

11. An integrated circuit as claimed in claim 8, wherein said plurality of processing stages are respective pipeline stages within a synchronous pipeline.

12. An integrated circuit as claimed in claim 8, wherein a maximum processing time taken for said processing operation is less than a sum of a time separating said delayed capture time from said non-delayed capture time and a time between non-delayed capture times such that said processing logic will have completed said processing operation by said delayed capture time.

13. An integrated circuit as claimed in claim 8, wherein said processing stages are part of a data processor.

14. An integrated circuit as claimed in claim 8, wherein when said comparator detects said change, said error-repair logic is operable to replace said non-delayed value with said delayed value as said processing stage output signal.

15. An integrated circuit as claimed in claim 14, wherein supply of said delayed value to said following processing stage forces forward progress through processing operations.

16. An integrated circuit as claimed in claim 8, wherein a minimum processing time taken for said processing operation is greater than a time separating said delayed capture time from said non-delayed capture time such that said delayed value is not influenced by a processing operation performed upon different input values.

17. An integrated circuit as claimed in claim 16, wherein said processing logic includes one or more delay elements to ensure said minimum processing time is exceeded.

18. An integrated circuit as claimed in claim 8, comprising an error counter circuit operable to store a count of detection of errors corresponding to said change.

19. An integrated circuit as claimed in claim 18, wherein said count may be read by software.

20. An integrated circuit as claimed in claim 8, wherein processing operations within said processing stage and said following processing stage are driven by a non-delayed clock signal.

21. An integrated circuit as claimed in claim 20, wherein when said comparator detects said change said error-repair logic is operable to gate said non-delayed clock signal to provide time for said following processing stage to recover from input of said non-delayed value and instead use said delayed value.

22. An integrated circuit as claimed in claim 21, wherein said non-delayed capture time is derived from a predetermined phase point of said non-delayed clock signal, a phased delayed version of said non-delayed clock signal is used as a delayed clock signal and said delayed capture time is derived from a predetermined phase point of said delayed clock signal.

23. A method of controlling an integrated circuit for performing data processing, said method comprising the steps of:

detecting errors in operation of said integrated circuit;

repairing detected errors in operation; and

controlling one or more performance controlling operational parameters of said integrated circuit;

wherein at least one of said one or more performance controlling parameters is controlled in dependence upon one or more characteristics of detected error such that a gain in one or more performance characteristics of said integrated circuit from operating with said one or more performance controlling parameters having values resulting in errors in operation of said integrated circuit exceeds a loss in said one or more performance characteristics from repairing errors in operation of said integrated circuit.

24. A method as claimed in claim 23, wherein said step of controlling applies feedback control to adjust said at least one of said one or more performance controlling parameters in dependence upon said one or more characteristics of detected errors.

25. A method as claimed in claim 23, wherein said one or more characteristics of detected errors comprise at least one of:

an error rate of detected errors; and

a reduction in computational throughput resulting from repair of detected errors.

26. A method as claimed in claim 23, wherein said one or more performance controlling parameters include at least one of:

an operating voltage;

an operating frequency;

an integrated circuit body bias voltage; and

temperature.

27. A method as claimed in claim 23, wherein said one or more performance characteristics comprise one or more of:

computational throughput, energy consumption and power.

28. A method as claimed in claim 23, wherein said step of detecting errors detects errors by double-sampling data signal values within said integrated circuit, a difference between sampled values being indicative of an error.

29. A method as claimed in claim 28, wherein said double-sampling is detecting a signal value at a sampling point at respective different times.

30. A method as claimed in claim 23 comprising the steps of:

supplying a processing stage output signal from at least one processing stage of a plurality of processing stages as a processing stage input signal to a following processing stage, said at least one processing stage operating to;

perform a processing operation with data processing logic upon at least one processing stage input value to generate a processing logic output signal;

capture a non-delayed value of said processing logic output signal at a non-delayed capture time, said non-delayed value being supplied to said following processing stage as said processing stage output signal following said non-delayed capture time; and

capture a delayed value of said processing logic output signal at a delayed capture time later than said non-delayed capture time;

wherein detecting errors comprises comparing said non-delayed value and said delayed value to detect a change in said processing logic output signal following said non-delayed capture time indicative of said processing logic not having finished said processing operation at said non-delayed capture time; and

said step of repairing detected errors comprises suppressing use of said non-delayed value by said following processing stage.

31. A method as claimed in claim 30, comprising detection meta-stability in said non-delayed value and triggering suppression of use of said non-delayed value if found to be meta-stable.

32. A method as claimed in claim 30, wherein when said change is detected, replacing said non-delayed value with said delayed value as said processing stage output signal.

33. A method as claimed in claim 30, wherein supply of said delayed value to said following processing stage forces forward progress through processing operations.

34. A method as claimed in claim 30, wherein when said change is detected, forcing said delayed value to be stored in place of said non-delayed value.

35. A method as claimed in claim 30, wherein said plurality of processing stages are respective pipeline stages within a synchronous pipeline.

36. A method as claimed in claim 30, wherein a maximum processing time taken for said processing operation is less than a sum of a time separating said delayed capture time from said non-delayed capture time and a time between non-delayed capture times such that said processing logic will have completed said processing operation by said delayed capture time.

37. A method as claimed in claim 30 wherein said processing stages are part of a data processor.

38. A method as claimed in claim 30, wherein a minimum processing time taken for said processing operation is greater than a time separating said delayed capture time from said non-delayed capture time such that said delayed value is not influenced by a processing operation performed upon different input values.

39. A method as claimed in claim 38, wherein said processing logic includes one or more delay elements to ensure said minimum processing time is exceeded.

40. A method as claimed in claim 30, comprising the step of storing a count of detection of errors corresponding to said change.

41. A method as claimed in claim 40, wherein said count may be read by software.

42. A method as claimed in claim 30, wherein processing operations within said processing stage and said following processing stage are driven by a non-delayed clock signal.

43. A method as claimed in claim 42, wherein when a change is detected at said comparing step said error-repair operation comprises gating said non-delayed clock signal to provide time for said following processing stage to recover from input of said non-delayed value and instead use said delayed value.

44. A method as claimed in claim 42, wherein said non-delayed capture time is derived from a predetermined phase point of said non-delayed clock signal, a phase delayed version of said non-delayed clock signal is used as a delayed clock signal and said delayed capture time is derived from a predetermined phase point of said delayed clock signal.

45. An integrated circuit for performing data processing, said integrated circuit comprising:

error detecting means for detecting errors in operation of said integrated circuit;

error-repair means for repairing errors in operation of said integrated circuit; and

operational parameter controlling means for controlling at least one of said one or more performance controlling parameters of said integrated circuit;

wherein

said operational parameter controlling means controls at least one of said one or more performance controlling parameters in dependence upon one or more characteristics of errors detected by said error detecting means such that a gain in one or more performance characteristics of said integrated circuit from operating with said one or more performance controlling parameters having values resulting in errors in operation of said integrated circuit exceeds a loss in one or more performance characteristics from repairing errors in operation of said integrated circuit with said error-repair means.