Pattern forming method and method for manufacturing semiconductor device

• US 8,409,786 B2
• Filed: 08/31/2007
• Issued: 04/02/2013
• Est. Priority Date: 05/24/2006
• Status: Expired due to Fees

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Yamamoto, Tomohiko, Asai, Satoru
• Primary Examiner(s): RAYMOND, BRITTANY L
• Application Number:
  US11/848,786
• Publication Number:
  US 20070298353A1
• Time in Patent Office: 2,041 Days
• Field of Search: 430/311, 430/5, 430/394
• US Class Current: 430/311
• CPC Class Codes: G03F 1/32 Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion,; Preparation thereof
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging

Abstract

Double exposure is performed by using a pair of photomasks, an attenuated phase shift mask or the like which is not an alternating phase shift mask, and a pattern is transferred onto a photoresist. Here, on the occasion of performing exposure with the photomask for forming a finer pattern, double pole illumination is used as an illumination system.

Claims

1. A manufacturing method of a semiconductor device, comprising:

a first mask pattern being formed on a first photomask and a second mask pattern being formed on a second photomask respectively,

wherein in at least one of the first photomask and the second photomask, a plurality of assist patterns which is not superimposed on the mask pattern of the other on an occasion of exposure and which is provided side by side as a striped pitch pattern in parallel with the first mask pattern or the second mask pattern is formed, and

said method further comprising,

a first exposing step of exposing the first mask pattern to a transfer object by using the first photomask; and

a second exposing step of exposing the second mask pattern to the transfer object so that at least a part of the second mask pattern is superimposed on the first mask pattern, by using the second photomask;

wherein in said second exposing step, the second mask pattern is exposed onto the transfer object by using a tri-tone mask in which a chrome mask and an attenuated phase shift mask are mixedly present, as the second photomask, and

wherein at least one of the first exposing step and the second exposing step is performed by using double pole illumination.

2. The manufacturing method of the semiconductor device according to claim 1,

wherein in the second photomask, a portion corresponding to the second mask pattern is made a half tone region, and a portion connected to an end portion of the second mask pattern is made a chrome region.

3. The manufacturing method of the semiconductor device according to claim 1,

wherein in said first exposing step, the first mask pattern has a first pattern extending in a first direction, and a second pattern extending in a second direction orthogonal to the first direction, and

wherein in said second exposing step, the second mask pattern has a third pattern extending in the first direction, which is exposed to be superimposed on the first pattern,

said method further comprising,

a third exposing step of exposing a fourth pattern extending in the second direction to the transfer object to be superimposed on the second pattern by using a third photomask,

wherein an illumination mode of the double pole illumination in said second exposing step, and an illumination mode of the double pole illumination in said third exposing step differ from each other.

4. The manufacturing method of the semiconductor device according to claim 3,

wherein in said second and third exposing steps, the second and a third mask patterns are exposed to the transfer object by using tri-tone masks in which chrome masks and attenuated phase shift masks are mixedly present respectively, as the second and the third photomasks.

5. The manufacturing method of the semiconductor device according to claim 4,

wherein in each of the second and third photomasks, a portion corresponding to the second mask pattern is made a half tone region, and a portion connected to an end portion of the second mask pattern is made a chrome region.

6. The manufacturing method of the semiconductor device according to claim 3,

wherein in at least one of the first photomask, the second photomask and the third photomask, an assist pattern which is not superimposed on the mask patterns of the other photomasks on an occasion of exposure is formed.

7. The manufacturing method of the semiconductor device according to claim 1,

wherein the assist patterns are transferred to the transfer object when exposed by solely using the photomask in which the assist patterns are formed.

8. The manufacturing method of the semiconductor device according to claim 1,

wherein the exposure is performed by using a polarized light illumination system having a function of the double pole illumination.

9. The manufacturing method of the semiconductor device according to claim 1,

wherein a plurality of the assist patterns which is in parallel with the first photomask pattern or the second photomask pattern is provided on the left side and the right side of the first photomask pattern or the second photomask pattern respectively, and the intervals between the adjacent assist patterns are the same.

10. A manufacturing method of a semiconductor device, comprising:

a first mask pattern being formed on a first photomask and a second mask pattern being formed on a second photomask respectively,

wherein in at least one of the first photomask and the second photomask, a plurality of assist patterns which is not superimposed on the mask pattern of the other on an occasion of exposure and which is provided side by side as a striped pitch pattern in parallel with the first mask pattern or the second mask pattern is formed,

said method further comprising,

a first exposing step of exposing a first pattern and a second pattern included in the first mask pattern and differing in extending direction to a transfer object by using the first photomask; and

a second exposing step of exposing a third pattern and a fourth pattern included in the second mask pattern to the transfer object so that at least a part of the first mask pattern is superimposed on the second mask by using the second photomask,

wherein in said second exposing step, the second mask pattern is exposed to the transfer object by using a tri-tone mask in which a chrome mask and an attenuated phase shift mask are mixedly present, as the second photomask, and

wherein at least one of said first exposing step and said second exposing step is performed by using quadrupole illumination.

11. The manufacturing method of the semiconductor device according to claim 10,

wherein the first pattern and the second pattern extend in directions orthogonal to each other, and the third pattern and the fourth pattern extend in directions orthogonal to each other.

12. The manufacturing method of the semiconductor device according to claim 10,

wherein in the second photomask, a portion corresponding to the second mask pattern is made a half tone region, and a portion connected to an end portion of the second mask pattern is made a chrome region.

13. The manufacturing method of the semiconductor device according to claim 10,

wherein the assist patterns are transferred to the transfer object when exposed by solely using the photomask in which the assist patterns are formed.

14. The manufacturing method of the semiconductor device according to claim 10,

wherein the exposure is performed by using a polarized light illumination system having a function of the quadrupole illumination.

15. The manufacturing method of the semiconductor device according to claim 10,

wherein a plurality of the assist patterns which is in parallel with the first photomask pattern or the second photomask pattern is provided on the left side and the right side of the first photomask pattern or the second photomask pattern respectively, and the intervals between the adjacent assist patterns are the same.