Semiconductor device manufacturing method

• US 8,409,930 B2
• Filed: 03/25/2011
• Issued: 04/02/2013
• Est. Priority Date: 03/27/2007
• Status: Expired due to Fees

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Inventors: Terui, Makoto, Shiraishi, Yasushi
• Primary Examiner(s): Clark, S. V.
• Assistant Examiner(s): SODERHOLM, KRISTA Z
• Application Number:
  US13/071,741
• Publication Number:
  US 20110171779A1
• Time in Patent Office: 739 Days
• Field of Search: 257/717, 257/E23.101, 438/108, 438/107, 438/122, 438/121, 438/106, 438/118
• US Class Current: 438/122
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/167 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A BGA substrate which has a back surface to which a heat radiating plate is attached and an opening for accommodating a relay wiring substrate therein, which is provided in the center of its surface, is used. The relay wiring substrate to which an ASIC chip and a memory chip are flip-chip connected, is bonded to the heat radiating plate in the opening with a thermal conductive bonding material. Further, each of the back surfaces of the ASIC chip and the memory chip is connected to a metal cap for sealing the opening through a thermal conductive material interposed therebetween.

Claims

1. A method for manufacturing a semiconductor device, comprising:

mounting a plurality of semiconductor chips over a relay wiring substrate by flip-chip connections;

bonding a heat radiating plate to a back surface of a main wiring substrate which has an opening therethrough;

bonding the relay wiring substrate equipped with the semiconductor chips to the heat radiating plate in the opening of the main wiring substrate using a bonding material having thermal conductivity;

connecting bonding wires between the relay wiring substrate and the main wiring substrate;

applying a thermal conductive material to each of back surfaces of the semiconductor chips; and

covering the opening of the main wiring substrate with a metal sealing plate, so that the metal sealing plate is connected to the semiconductor chips by the thermal conductive material.

2. The method for manufacturing a semiconductor device of claim 1, wherein the semiconductor chips comprise a first chip that is an application specific integrated circuit (ASIC) chip and a second chip that is a memory chip.

3. The method for manufacturing a semiconductor device of claim 1, wherein the thermal conductive material comprises thermal conductive grease.

4. The method for manufacturing a semiconductor device of claim 1, wherein the thermal conductive material comprises thermal conductive gel.

5. The method for manufacturing a semiconductor device of claim 1, further comprising disposing the main wiring substrate on a mounting board by soldering the metal sealing plate directly to a ground wire of the mounting board.

6. The method for manufacturing a semiconductor device of claim 1, wherein the main wiring substrate is configured as a ball grid array substrate.

7. The method for manufacturing a semiconductor device of claim 1, wherein the heat radiating plate comprises copper.

8. A method for manufacturing a semiconductor device, comprising:

mounting a plurality of semiconductor chips over a relay wiring substrate by flip-chip connections;

bonding a heat radiating plate to a back surface of a main wiring substrate which has an opening therethrough;

bonding the relay wiring substrate equipped with the semiconductor chips to the heat radiating plate in the opening of the main wiring substrate using a bonding material having thermal conductivity;

connecting bonding wires between the relay wiring substrate and the main wiring substrate;

filling the opening of the main wiring substrate with a thermal conductive material; and

covering the opening of the main wiring substrate with a metal sealing plate.

9. The method for manufacturing a semiconductor device of claim 8, wherein the semiconductor chips comprise a first chip that is an application specific integrated circuit (ASIC) chip and a second chip that is a memory chip.

10. The method for manufacturing a semiconductor device of claim 8, wherein the thermal conductive material comprises thermal conductive resin.

11. The method for manufacturing a semiconductor device of claim 8, wherein the thermal conductive material comprises thermal conductive oil.

12. The method for manufacturing a semiconductor device of claim 8, further comprising disposing the main wiring substrate on a mounting board by soldering the metal sealing plate directly to a ground wire of the mounting board.

13. The method for manufacturing a semiconductor device of claim 8, wherein the main wiring substrate is configured as a ball grid array substrate.

14. The method for manufacturing a semiconductor device of claim 8, wherein the heat radiating plate comprises copper.

15. A method for manufacturing a semiconductor device, comprising:

mounting a plurality of semiconductor chips over a relay wiring substrate by flip-chip connections;

bonding a heat radiating plate to a back surface of a main wiring substrate which has an opening therethrough;

bonding the relay wiring substrate equipped with the semiconductor chips to the heat radiating plate in the opening of the main wiring substrate using a bonding material having thermal conductivity;

connecting bonding wires between the relay wiring substrate and the main wiring substrate; and

attaching a metal sealing plate to the main wiring substrate to cover the opening and so that the metal sealing plate is in thermal contact with the semiconductor chips via a thermal conductive material.

16. The method for manufacturing a semiconductor device of claim 15, wherein the thermal conductive material is disposed only as substantially sandwiched between the metal sealing plate and the semiconductor chips.

17. The method for manufacturing a semiconductor device of claim 16, wherein the thermal conductive material is one of thermal conductive grease and thermal conductive gel.

18. The method for manufacturing a semiconductor device of claim 15, wherein the opening is filled with the thermal conductive material.

19. The method for manufacturing a semiconductor device of claim 18, wherein the thermal conductive material comprises one of thermal conductive resin and thermal conductive oil.

20. The method for manufacturing a semiconductor device of claim 15, further comprising disposing the main wiring substrate on a mounting board by soldering the metal sealing plate directly to a ground wire of the mounting board.