Semiconductor device and method of making integrated passive devices

• US 8,409,970 B2
• Filed: 12/03/2007
• Issued: 04/02/2013
• Est. Priority Date: 10/29/2005
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Lin, Yaojian, Cao, Haijing, Zhang, Qing, Chen, Kang, Fang, Jianmin
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US11/949,255
• Publication Number:
  US 20090140421A1
• Time in Patent Office: 1,947 Days
• Field of Search: 438/118, 438/125, 438/393, 438/384, 438/459, 438/464, 257/E21.508, 257/E21.511
• US Class Current: 438/464
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization.

Claims

1. A method of making a semiconductor device, comprising:

providing a silicon semiconductor substrate;

forming passive circuit elements including a capacitor and inductor over the silicon semiconductor substrate by,

(a) forming a first insulating layer over the silicon semiconductor substrate,

(b) forming a first conductive layer over the first insulating layer,

(c) forming a second insulating layer over the first conductive layer,

(d) forming a second conductive layer over the second insulating layer,

(e) forming a third conductive layer over the first insulating layer and disposed apart from the first conductive layer,

(f) forming a first passivation layer over the first, second, and third conductive layers,

(g) forming a fourth conductive layer over the first passivation layer, the fourth conductive layer including individual portions in electrical contact with the second and third conductive layers to form multiple passive circuit elements,

(h) forming a second passivation layer over the fourth conductive layer and first passivation layer, and

(i) removing a portion of the second passivation layer to expose the fourth conductive layer;

attaching a carrier to the second passivation layer opposite the silicon semiconductor substrate;

removing the silicon semiconductor substrate with back grinding, silicon wet etching, plasma etching, or chemical mechanical polishing (CMP) to expose the first insulating layer;

disposing a non-silicon substrate over the first insulating layer opposite the second passivation layer;

removing the carrier;

forming an electrical interconnect over the second passivation layer; and

singulating the non-silicon substrate.

2. The method of claim 1, wherein the non-silicon substrate is made with a material selected from the group consisting of glass, molding compound, epoxy, polymer, and polymer composite.

3. The method of claim 2, wherein the non-silicon substrate is made of a material with a resistivity of approximately 1000 ohm-cm.

4. The method of claim 1, wherein the fourth conductive layer is coiled on the first passivation layer to have an inductive property.

5. The method of claim 1, wherein the first and second conductive layers and the second insulating layer have a capacitive property.

6. The method of claim 1, further including:

forming an under bump metallization over the second passivation layer; and

forming a bump on the under bump metallization.

7. The method of claim 1, further including forming a resistive layer over the first insulating layer.

8. method of making a semiconductor device, comprising:

providing a silicon semiconductor substrate;

forming a passive circuit element over the silicon semiconductor substrate, including;

forming a first insulating layer over the silicon semiconductor substrate,

forming a first conductive layer over the first insulating layer,

forming a first passivation layer over the first conductive layer,

forming a second conductive layer over the first passivation layer in electrical contact with the first conductive layer and coiled to exhibit an inductive property, and

forming a second passivation layer over the first passivation layer and second conductive layer;

attaching a carrier to the second passivation layer opposite the silicon semiconductor substrate;

removing the silicon semiconductor substrate to expose the first insulating layer;

disposing a non-silicon substrate over the first insulating layer opposite the second passivation layer;

removing the carrier; and

singulating the non-silicon substrate.

9. The method of claim 8, wherein the non-silicon substrate is made with a material selected from the group consisting of glass, molding compound, epoxy, polymer, and polymer composite.

10. The method of claim 8, further including:

forming a third conductive layer over the first insulating layer and disposed apart from the first conductive layer;

forming a second insulating layer over the third conductive layer; and

forming a fourth conductive layer over the second insulating layer, the fourth conductive layer including individual portions in electrical contact with the second and third conductive layers.

11. The method of claim 10, wherein the third and fourth conductive layers and the second insulating layer have a capacitive property.

12. The method of claim 8, further including:

forming an under bump metallization over the second passivation layer; and

forming a bump on the under bump metallization.

13. The method of claim 8, further including forming a resistive layer over the first insulating layer.

14. A method of making a semiconductor device, comprising:

providing a silicon substrate;

forming a first insulating layer over the silicon substrate;

forming an integrated passive device including an inductor or capacitor over the first insulating layer;

forming a second insulating layer over the integrated passive device;

attaching a carrier to the second insulating layer;

removing the silicon substrate to expose the first insulating layer;

forming a non-silicon substrate over the first insulating layer opposite the carrier; and

removing the carrier.

15. The method of claim 14, wherein the non-silicon substrate is made with a material selected from the group consisting of glass, molding compound, epoxy, polymer, and polymer composite.

16. The method of claim 14, further including:

forming an under bump metallization over the second insulating layer in electrical contact with the integrated passive device; and

forming a bump on the under bump metallization.

17. A method of making a semiconductor device, comprising:

providing a silicon substrate;

forming a first insulating layer over the silicon substrate;

forming a first conductive layer over the first insulating layer;

forming a first passivation layer over the first conductive layer;

forming a second conductive layer over the first passivation layer in electrical contact with the first conductive layer;

forming a second passivation layer over the second conductive layer, wherein the first and second conductive layers, and first and second passivation layers form a passive circuit element;

attaching a carrier over the second passivation layer opposite the silicon substrate;

removing the silicon substrate to expose the first insulating layer;

disposing a non-silicon substrate over the first insulating layer opposite the second passivation layer;

removing the carrier; and

singulating the non-silicon substrate.

18. The method of claim 17, wherein the non-silicon substrate is made with a material selected from the group consisting of glass, molding compound, epoxy, polymer, and polymer composite.

19. The method of claim 17, further including:

forming a third conductive layer over the first insulating layer and disposed apart from the first conductive layer;

forming a second insulating layer over the third conductive layer; and

forming a fourth conductive layer over the second insulating layer, the fourth conductive layer including individual portions in electrical contact with the second and third conductive layers.

20. The method of claim 19, wherein the third and fourth conductive layers and the second insulating layer have a capacitive property.

21. The method of claim 17, wherein the second conductive layer is coiled on the first passivation layer to have an inductive property.

22. The method of claim 17, further including:

forming an under bump metallization over the second passivation layer; and

forming a bump on the under bump metallization.

23. The method of claim 17, further including forming a resistive layer over the first insulating layer.

24. A method of making a semiconductor device, comprising:

providing a semiconductor substrate including a first insulating layer;

forming an integrated passive device having capacitive properties or inductive properties over the semiconductor substrate;

forming a second insulating layer over the integrated passive device;

removing the semiconductor substrate to expose the first insulating layer; and

forming a non-silicon substrate over the integrated passive device and first insulating layer.

25. The method of claim 24, further including forming a resistive layer over the first insulating layer.

26. The method of claim 24, wherein the non-silicon substrate is made with a material selected from the group consisting of glass, molding compound, epoxy, polymer, and polymer composite.

27. The method of claim 24, wherein the non-silicon substrate is made of a material with a resistivity of approximately 1000 ohm-cm.

28. The method of claim 24, wherein the integrated passive device includes an inductor, capacitor, or resistor.

29. The method of claim 24, wherein forming the integrated passive device includes:

forming a first conductive layer over the first insulating layer;

forming a third insulating layer over the first conductive layer; and

forming a second conductive layer over the third insulating layer.

30. The method of claim 29, wherein forming the integrated passive device further includes forming a third conductive layer over the second insulating layer, the third conductive layer being coiled to have an inductive property.

31. The method of claim 24, further including forming an interconnect structure over the second insulating layer and electrically connected to the integrated passive device.

32. The method of claim 31, wherein forming the interconnect structure includes:

forming an under bump metallization over the second insulating layer in electrical contact with the integrated passive device; and

forming a bump on the under bump metallization.