Structure and method to fabricate a body contact

• US 8,409,989 B2
• Filed: 11/11/2010
• Issued: 04/02/2013
• Est. Priority Date: 11/11/2010
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Pei, Chengwen, Booth, Roger Allen Jr., Cheng, Kangguo, Ervin, Joseph, Todi, Ravi M., Wang, Geng
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US12/944,174
• Publication Number:
  US 20120119310A1
• Time in Patent Office: 873 Days
• Field of Search: 438/149, 438/643, 438/647, 438/649, 438/855, 438/657, 438/682, 257/347, 257/401, 257/413, 257/751, 257/755, 257/774, 257/778
• US Class Current: 438/682
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Abstract

A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.

Claims

1. A method for fabricating a body contact on a transistor having a body, source, drain, and gate, the transistor disposed on a dielectric layer, comprising:

forming a cavity in the dielectric layer to expose a portion of the body of the transistor;

forming a silicide layer on the exposed portion of the body;

depositing a metal liner on the silicide layer;

and depositing a layer of polysilicon on the metal liner.

2. The method of claim 1, further comprising:

disposing the dielectric layer on a handle wafer;

inverting the handle wafer; and

removing the handle wafer, prior to forming a cavity in the dielectric layer to expose a portion of the body of the transistor.

3. The method of claim 2, further comprising:

applying a mask layer over the dielectric layer;

lithographically patterning the mask layer to form a void in the mask layer, above the exposed portion of the body; and

wherein forming a cavity in the dielectric layer to expose a portion of the body of the transistor comprises etching the dielectric layer.

4. The method of claim 3, wherein etching the dielectric layer is performed with a reactive ion etch.

5. The method of claim 3, further comprising removing the mask layer after etching the dielectric layer.

6. The method of claim 1, wherein forming a silicide layer comprises forming a nickel silicide layer.

7. The method of claim 1, wherein forming a silicide layer comprises forming a cobalt silicide layer.

8. The method of claim 1, wherein the step of depositing a metal liner comprises depositing a liner comprising titanium.

9. The method of claim 1, wherein depositing a metal liner comprises depositing a liner comprising copper.

10. The method of claim 1, wherein depositing a metal liner is performed via atomic layer deposition.

11. The method of claim 1, wherein depositing a metal liner is performed via chemical vapor deposition.

12. A method for fabricating a body contact on a transistor having a body, source, drain, and gate, the transistor disposed on a dielectric layer, comprising:

forming a cavity in the dielectric layer to expose a portion of the body of the transistor;

forming a cavity in the dielectric layer to expose an active silicon area;

forming a silicide layer on the exposed portion of the body;

depositing a metal liner on the silicide layer;

depositing a polysilicon layer on the metal liner; and

forming a void in the polysilicon layer, the void disposed between the body and the active silicon area.