Semiconductor device which can transmit electrical signals between two circuits

• US 8,410,493 B2
• Filed: 03/11/2010
• Issued: 04/02/2013
• Est. Priority Date: 03/13/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Nakashiba, Yasutaka
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): Malek, Maliheh
• Application Number:
  US12/722,092
• Publication Number:
  US 20100230783A1
• Time in Patent Office: 1,118 Days
• Field of Search: 438/171, 438/190, 438/210, 438/238, 438/329, 438/381, 438/24, 438/59, 257/531, 257/E21.022, 257/80, 257/83, 340/572.1, 340/572.2, 340/572.4, 439/66, 439/950
• US Class Current: 257/80
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12041 LED

Abstract

A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit.

Claims

1. A semiconductor device comprising:

a first substrate;

a second substrate;

a multi-level interconnect structure provided over the first substrate;

a first inductor provided in the multi-level interconnect structure so as to surround all transistors provided over the first substrate in a plan view; and

a second inductor provided in the multi-level interconnect structure so as to surround all the transistors provided over the first substrate in the plan view,

wherein the second inductor is provided over the first inductor,

wherein the first substrate is provided with a first circuit region containing a first circuit,

wherein the second substrate is provided with a second circuit region containing a second circuit,

wherein the first inductor is provided in the multi-level interconnect structure so as to include the first circuit region,

wherein the second inductor is provided in the multi-level interconnect structure so as to include the first circuit region, and

wherein one of the first inductor and the second inductor is connected to the first circuit, and the other of the first inductor and the second inductor is connected to the second circuit.

2. The semiconductor device according to claim 1, wherein the first inductor and the second inductor differ from each other in reference voltage.

3. The semiconductor device according to claim 1,

wherein the multi-level interconnect structure includes a first interconnect layer, an insulation layer placed on the first interconnect layer, and a second interconnect layer placed on the insulation layer,

wherein the first inductor is provided on the first interconnect layer, and

wherein the second inductor is provided on the second interconnect layer.

4. The semiconductor device according to claim 1, wherein the first inductor and the second inductor overlap each other in the plan view.

5. The semiconductor device according to claim 3, wherein spacing between the first inductor and the second inductor is smaller than diameters of the first inductor and the second inductor.

12. The semiconductor device according to claim 1, further comprising:

pads provided in a top of the multi-level interconnect structure,

wherein all the pads are surrounded by the first inductor and the second inductor in the plan view.

13. The semiconductor device according to claim 12, wherein the pads are connected to the transistors.

14. The semiconductor device according to claim 13, wherein the pads are connected to other regions across the second inductor.

6. A semiconductor device, comprising:

a first substrate, provided with a first circuit region containing a first circuit;

a second circuit region, on the first substrate, containing a second circuit;

a multi-level interconnect structure provided over the first substrate;

a first inductor provided in the multi-level interconnect structure so as to surround all transistors provided over the first substrate in a plan view; and

a second inductor provided in the multi-level interconnect structure so as to surround all the transistors provided over the first substrate in the plan view,

wherein the second inductor is provided over the first inductor,

wherein the first circuit region and the second circuit region are insulated from each other,

wherein the first inductor is provided in the multi-level interconnect structure so as to include the first circuit region,

wherein the second inductor is provided in the multi-level interconnect structure so as to include the first circuit region, and

wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit.

7. The semiconductor device according to claim 6, wherein the first circuit is a transmit circuit including a transmit driver circuit connecting to the first inductor.

8. The semiconductor device according to claim 7, wherein one end of the first inductor is connected to the transmit driver circuit and another end of the first inductor is connected to a power wire or a ground wire.

9. The semiconductor device according to claim 6, wherein the second circuit includes a receive circuit and a receive driver circuit.

10. The semiconductor device according to claim 9, further comprising:

wiring which connects the second inductor and the second circuit with each other.

11. The semiconductor device according to claim 10, wherein the first circuit region is located inside an area surrounded by the first inductor and the second inductor.