finFETs and methods of making same

• US 8,410,544 B2
• Filed: 09/09/2011
• Issued: 04/02/2013
• Est. Priority Date: 09/17/2009
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Kevin K., Kanarsky, Thomas Safron, Li, Jinghong, Ouyang, Christine Qiqing, Park, Dae-Gyu, Ren, Zhibin, Wang, Xinhui, Yin, Haizhou
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US13/228,519
• Publication Number:
  US 20110316081A1
• Time in Patent Office: 571 Days
• Field of Search: 438/300, 257/328, 257/331, 257/401, 257/E29.022, 257/E29.024
• US Class Current: 257/328
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.

Claims

1. A structure, comprising:

two or more silicon fins on a top surface of an insulating layer, said insulating layer on a silicon substrate, each fin of said two or more fins having opposite sidewalls connecting opposite first and second ends;

a gate dielectric layer on said sidewalls of each fin of said two or more fins;

an electrically conductive gate over said gate dielectric layer;

first and second regions of said silicon substrate on opposite sides of said gate;

a first merged source/drain comprising first epitaxial silicon regions extending from said first region of said silicon substrate, through said insulating layer, and abutting second epitaxial regions extending from said first ends of each fin of said two or more fins; and

a second merged source/drain comprising third epitaxial silicon regions extending from said second region of said silicon substrate, through said insulating layer, and abutting fourth epitaxial regions extending from said second ends of each fin of said two or more fins.

2. The structure of claim 1, wherein said insulating layer has a thickness between about 20 nm and about 40 nm.

3. The structure of claim 1, further including:

dielectric caps on respective top surfaces of each fin of said two or more fins, said dielectric caps between said respective top surfaces of each fin of said two or more fins and said gate dielectric layer.

4. The structure of claim 1, further including:

an electrically conductive depletion stop layer on said gate dielectric layer.

5. The structure of claim 1, further including:

a first P-well or N-well in said first silicon region of said substrate; and

a second P-well or N-well in said second silicon region of said substrate.

6. The structure of claim 1, further including:

recesses part way through said insulating layer, said recesses adjacent to respective sides of each fin of said two or more fins.

7. The structure of claim 1, further including:

recesses part way through said silicon substrate in said first and second regions of said silicon substrate.

8. The structure of claim 1, wherein said gate dielectric comprises material having a relative permittivity above about 10 and selected from the group consisting of metal oxides, Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, Al₂O₃, metal silicates, HfSi_xO_y or HfSi_xO_yN_z or combinations thereof.

9. The structure of claim 1, wherein surfaces of said first and second regions of said silicon substrate are coplanar with a {100} crystal plane of said silicon substrate and said first and second ends of said each fin of said two or more fins are coplanar with a {110} crystal plane of each fin of said two or more fins.

10. The structure of claim 1, wherein said two or more fins are regions of a silicon layer of a silicon-on insulator substrate, said silicon-on-insulator substrate comprising said silicon layer, separated from said silicon substrate by said insulating layer, said insulating layer comprising silicon oxide.

11. The structure of claim 1, further including:

a dielectric spacer on sidewalls of said first merged source/drain and second merged source/drain.

12. The structure of claim 1, wherein said gate dielectric is between 0.5 nm and 20 nm thick.

13. The structure of claim 4, wherein said stop layer comprises a material selected from the group consisting of Ti, Ta, W, TiN and TaN.

14. The structure of claim 4, wherein said stop layer is between 0.5 nm and 20 nm thick.

15. The structure of claim 3, wherein said dielectric caps have a thickness no greater than 200 nm.

16. The structure of claim 10, wherein insulating layer has a thickness between 20 nm and 40 nm.

17. The structure of claim 10, wherein silicon layer has a thickness between 5 nm and 100 nm.

18. The structure of claim 1, wherein each fin of said two or more fins comprise a tri-gated finFET.

19. The structure of claim 3, wherein each fin of said two or more fins comprise a dual-gated finFET.

20. The structure of claim 1, wherein said two or more fins each have a width between 5 nm and 40 nm and are spaced apart a distance between 15 nm and 100 nm.