Semiconductor device and method of manufacturing the same

• US 8,410,557 B2
• Filed: 06/17/2009
• Issued: 04/02/2013
• Est. Priority Date: 06/27/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Yoneda, Haruki, Sasada, Kazuhiro
• Primary Examiner(s): Toledo, Fernando L.
• Assistant Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US12/486,062
• Publication Number:
  US 20090321852A1
• Time in Patent Office: 1,385 Days
• Field of Search: 257/491, 257/492
• US Class Current: 257/409
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A P type drift layer is formed in an N type epitaxial layer from under a drain layer to under an N type body layer under a source layer through under an element isolation insulation film. This P type drift layer is shallower immediately under the drain layer than under the element isolation insulation film, and gradually shallows from under the element isolation insulation film to the N type body layer to be in contact with the bottom of the N type body layer. Since the P type drift layer is thus diffused in a wide region, a wide current path is formed from the N type body layer to the drain layer, and the current drive ability is enhanced and the drain breakdown voltage is also increased.

Claims

1. A semiconductor device comprising:

a semiconductor layer of a first conductive type;

an element isolation insulation film formed on a front surface of said semiconductor layer;

a body layer of the first conductive type formed on the front surface of said semiconductor layer near one end of said element isolation insulation film;

a drain layer of a second conductive type formed on the front surface of said semiconductor layer near other end of said element isolation insulation film;

a source layer of the second conductive type formed on a front surface of said body layer;

a gate insulation film formed on said body layer;

a gate electrode extending from on said element isolation insulation film onto said body layer with said gate insulation film being interposed therebetween; and

a drift layer expanding in said semiconductor layer from under said drain layer to under said body layer that is under said source layer,

wherein said drift layer is shallower immediately under said drain layer than under said element isolation insulation film, and gradually becomes shallower from under said element isolation insulation film to said body layer to be in contact with a bottom of said body layer, and in a sectional view of the semiconductor device, the drift layer has a depth profile that is curved to have a peak under the element isolation insulation film and is not flat under the element isolation insulation film,

wherein said drift layer under said drain layer is superposed with other drift layer next thereto.

2. The semiconductor device of claim 1, wherein said drift layer under said body layer is not superposed with other drift layer next thereto.

3. The semiconductor device of claim 1, wherein said body layer comprises a channel layer of the first conductive type formed on the front surface of said body layer, and a concentration of said channel layer is higher than a concentration of said body layer.