Semiconductor device packages with electromagnetic interference shielding

• US 8,410,584 B2
• Filed: 04/29/2009
• Issued: 04/02/2013
• Est. Priority Date: 08/08/2008
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: An, JaeSeon, Lee, Jeong, Cha, SangJin, Youn, SungHo
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): FERNANDES, ERROL V
• Application Number:
  US12/432,621
• Publication Number:
  US 20100032815A1
• Time in Patent Office: 1,434 Days
• Field of Search: 257/659, 257/660, 257/704, 257/706, 257/796, 361/748, 361/818, 438/113, 438/119, 438/127
• US Class Current: 257/660
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/15159 : Side view
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element disposed adjacent to a periphery of the substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit; (2) a semiconductor device disposed adjacent to the upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body. A periphery of the package body is laterally recessed, such that a connection surface of the grounding element is electrically exposed and electrically connected to the EMI shield. The grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Claims

1. A semiconductor package, comprising:

a substrate including

an upper surface,

a lower surface, and

a grounding element disposed adjacent to a periphery of the substrate and at least partially extending between the upper surface and the lower surface of the substrate, the grounding element including a connection surface disposed adjacent to and extending downwardly from a substantially planar portion of the upper surface of the substrate, wherein the connection surface is a curved surface extending outwardly from the substantially planar portion;

a package body disposed adjacent to the upper surface of the substrate, a periphery of the package body being laterally recessed with respect to the periphery of the substrate, such that the connection surface of the grounding element is exposed; and

an electromagnetic interference shield disposed adjacent to the package body and physically connected to the connection surface of the grounding element,

wherein the grounding element provides an electrical pathway to ground.

2. The semiconductor package of claim 1, wherein the grounding element includes a via pad, and the connection surface of the grounding element includes an exposed lateral surface of the via pad.

3. The semiconductor package of claim 2, wherein the electromagnetic interference shield is physically connected to the exposed lateral surface of the via pad.

4. The semiconductor package of claim 1, further comprising a plurality of grounding elements including the grounding element, the plurality of grounding elements positioned around a periphery of the substrate and electrically connected to the electromagnetic interference shield.

5. The semiconductor package of claim 1, wherein the electromagnetic interference shield includes a curved portion that extends along the connection surface.

6. The semiconductor package of claim 5, wherein the curved portion terminates substantially at a periphery of the grounding element.

7. The semiconductor package of claim 1, wherein:

the grounding element includes a first surface at the periphery of the substrate; and

the connection surface is recessed relative to the first surface of the grounding element.

8. The semiconductor package of claim 1, wherein the grounding element corresponds to a remnant of a grounding via and the connection surface of the grounding element is disposed adjacent to a peripheral portion of the upper surface of the substrate.

9. A semiconductor package, comprising:

a substrate including

a first surface,

a second opposing surface, and

a grounding element at least partially extending between the first surface and the second opposing surface of the substrate, the grounding element corresponding to a remnant of a grounding via and including a connection surface disposed adjacent to a peripheral portion of the first surface of the substrate, wherein the connection surface is a curved surface having a concave profile extending from the first surface;

a package body disposed adjacent to the first surface of the substrate, a periphery of the package body being recessed with respect to a periphery of the substrate, such that the connection surface of the grounding element is exposed adjacent to the peripheral portion of the first surface of the substrate; and

an electromagnetic interference shield disposed adjacent to the package body and directly connected to the connection surface of the grounding element.

10. The semiconductor package of claim 9, wherein the grounding element includes a via pad remnant having a lateral surface which forms a portion of the grounding element.

11. The semiconductor package of claim 9, further comprising a plurality of grounding elements including the grounding element, the plurality of grounding elements positioned around a periphery of the substrate and electrically connected to the electromagnetic interference shield.

12. The semiconductor package of claim 9, wherein the grounding element includes a plated channel remnant, wherein the plated channel remnant at least partially extends between the first surface and the second opposing surface of the substrate.

13. The semiconductor package of claim 9, wherein the electromagnetic interference shield includes a lateral curved portion that extends along the connection surface.

14. The semiconductor package of claim 9, wherein the electromagnetic interference shield includes a first layer and a second layer disposed adjacent to the first layer, and the first layer and the second layer include different electrically conductive materials.

15. The semiconductor package of claim 9, wherein:

the grounding element includes a third surface at the periphery of the substrate; and

the connection surface is recessed relative to the third surface of the grounding element.

16. A semiconductor package, comprising:

a substrate including an upper surface, a lower surface, and a grounding element at least partially extending between the upper surface and the lower surface of the substrate, the grounding element including a first surface and a second surface, and at least a portion of the first surface is exposed at a periphery of the substrate, wherein the first surface is a curved surface having a concave profile extending from the upper surface of the substrate, and wherein the first surface is adjacent to the upper surface of the substrate, the second surface is adjacent to the lower surface of the substrate, and the first surface is recessed relative to the second surface;

a package body disposed adjacent to the upper surface of the substrate; and

an electromagnetic interference shield disposed adjacent to the package body and electrically connected to at least the first surface of the grounding element.

17. The semiconductor package of claim 16, wherein the grounding element includes a via pad remnant having a lateral surface which forms a portion of the grounding element.

18. The semiconductor package of claim 16, further comprising a plurality of grounding elements including the grounding element, the plurality of grounding elements positioned around a periphery of the substrate and electrically connected to the electromagnetic interference shield.

19. The semiconductor package of claim 16, wherein the grounding element includes a plated channel remnant, wherein the plated channel remnant at least partially extends between the upper surface and the lower surface of the substrate.

20. The semiconductor package of claim 16, wherein the electromagnetic interference shield includes a lateral curved portion that extends along the first surface.

21. The semiconductor package of claim 16, wherein the electromagnetic interference shield includes a first layer and a second layer disposed adjacent to the first layer, and the first layer and the second layer include different electrically conductive materials.

22. The semiconductor package of claim 16, wherein the grounding element corresponds to a remnant of a grounding via and the first surface of the grounding element includes a connection surface disposed adjacent to a peripheral portion of the upper surface of the substrate.