Transistor arrangement and integrated circuit
First Claim
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1. A transistor arrangement, comprising:
- a switch transistor comprising a charge storing structure and a control structure; and
a sense transistor comprising a charge storing structure, a control structure and a select structure;
wherein the control structure of the switch transistor and the control structure of the sense transistor each comprise a control gate;
wherein the select structure of the sense transistor comprises a select gate;
wherein the charge storing structure of the switch transistor is electrically connected to the charge storing structure of the sense transistor; and
wherein the sense transistor is configured such that the select structure and the control structure of the sense transistor may be electrically controlled independently from one another.
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Abstract
A transistor arrangement includes a switch transistor and a sense transistor. The switch transistor includes a charge storing structure and a control structure. The sense transistor includes a charge storing structure, a control structure and a select structure. The charge storing structure of the switch transistor is electrically connected to the charge storing structure of the sense transistor. The sense transistor is configured such that the select structure and the control structure of the sense transistor may be electrically controlled independently from one another.
14 Citations
24 Claims
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1. A transistor arrangement, comprising:
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a switch transistor comprising a charge storing structure and a control structure; and a sense transistor comprising a charge storing structure, a control structure and a select structure; wherein the control structure of the switch transistor and the control structure of the sense transistor each comprise a control gate; wherein the select structure of the sense transistor comprises a select gate; wherein the charge storing structure of the switch transistor is electrically connected to the charge storing structure of the sense transistor; and wherein the sense transistor is configured such that the select structure and the control structure of the sense transistor may be electrically controlled independently from one another. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An integrated circuit, comprising:
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a plurality of field programmable gate array cells electrically connected to one another, wherein each field programmable gate array cell of the plurality of field programmable gate array cells comprises; a transistor arrangement, comprising; a switch transistor comprising a charge storing structure and a control structure; and a sense transistor comprising a charge storing structure, a control structure and a select structure; wherein the control structure of the switch transistor and the control structure of the sense transistor each comprise a control gate; wherein the select structure of the sense transistor comprises a select gate; wherein the charge storing structure of the switch transistor is electrically connected to the charge storing structure of the sense transistor; and wherein the sense transistor is configured such that the select structure and the control structure of the sense transistor may be electrically controlled independently from one another. - View Dependent Claims (16)
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17. A transistor arrangement, comprising:
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a 1-transistor type switch device comprising a floating gate and a control gate; and a 2-transistor type sense device comprising a floating gate, a control gate and a select gate; wherein the floating gate of the switch device is electrically connected to the floating gate of the sense device; and wherein the sense device is configured such that the select gate and the control gate of the sense device may be controlled independently from one another. - View Dependent Claims (18, 19, 20, 21, 22)
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23. An integrated circuit, comprising:
a plurality of field programmable gate array cells electrically connected to one another, wherein each field programmable gate array cell of the plurality of field programmable gate array cells comprises; a transistor arrangement, comprising; a 1-transistor type switch device comprising a floating gate and a control gate; and a 2-transistor type sense device comprising a floating gate, a control gate and a select gate; wherein the floating gate of the switch device is electrically connected to the floating gate of the sense device; and wherein the sense device is configured such that the select gate and the control gate of the sense device may be controlled independently from one another. - View Dependent Claims (24)
Specification