Shielding black reference pixels in image sensors

• US 8,411,174 B2
• Filed: 03/07/2011
• Issued: 04/02/2013
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ovsiannikov, Ilia
• Primary Examiner(s): MOE, AUNG SOE
• Application Number:
  US13/041,795
• Publication Number:
  US 20110205405A1
• Time in Patent Office: 757 Days
• Field of Search: 348/245, 348/243, 348/244, 348/246, 348/308, 382/275, 382/254, 257/446, 257/234, 257/291
• US Class Current: 348/245
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H04N 25/621 for the control of blooming

Abstract

An image sensor having an array of pixel cells, each including a photo-conversion device. The array has first, second, and third groups of pixel cells. The first group of pixel cells receives light and the second and third groups are shielded from light. Each pixel cell of the second group is configured to output a black reference signal for determining a black level of the array. Each pixel cell of the third group has at least one first transistor coupled to the photo-conversion device, and each transistor coupled to the photo-conversion device has a gate coupled to a power supply voltage.

Claims

1. A guard pixel cell comprising:

a photo-conversion device;

a first transistor connected to the photo-conversion device, the first transistor having a gate coupled to a power supply voltage;

a second transistor having a gate coupled to the photo-conversion device, a first source/drain region coupled to the power supply voltage, and a second source/drain region coupled to a third transistor, the third transistor having a source/drain region coupled to a column output line.

2. The pixel cell of claim 1, wherein the third transistor comprises a gate coupled to a ground potential.

3. A guard pixel cell comprising:

a photo-conversion device;

a first transistor connected to the photo-conversion device and a floating diffusion region, the first transistor having a gate coupled to a power supply voltage;

a second transistor connected to the floating diffusion region, the second transistor having a gate and a source/drain region coupled to the power supply voltage; and

a third transistor having a gate coupled to the floating diffusion region, a first source/drain region coupled to the power supply voltage, and a second source/drain region coupled to a fourth transistor, the fourth transistor having a source/drain region coupled to a column output line.

4. The pixel cell of claim 3, wherein the fourth transistor comprises a gate coupled to a ground potential.

5. An image sensor comprising:

an array of pixel cells, the array comprising first, second, and third groups of pixel cells, the first group for receiving light, the second and third groups shielded from light, each pixel cell of the second group configured to output a black reference signal for determining a black level of the array and each pixel cell of the third group comprising a photo-conversion device and at least one first transistor coupled to the photo-conversion device for dissipating charge therefrom, each first transistor coupled to the photo-conversion device having a gate coupled to a power supply voltage.

6. The image sensor of claim 5, wherein at least one first transistor is connected to the photo-conversion device.

7. The image sensor of claim 5, further comprising a second transistor, the second transistor having a source/drain region coupled to a column output line.

8. The image sensor of claim 7, wherein the second transistor further comprises a gate coupled to a ground potential.

9. The image sensor of claim 5, wherein there is one first transistor coupled to the photo-conversion device.

10. The image sensor of claim 9, wherein the first transistor is a reset transistor.

11. The image sensor of claim 9, wherein the first transistor is a transfer transistor.

12. The image sensor of claim 9, wherein the first transistor comprises a source/drain region coupled to the power supply.

13. The image sensor of claim 9, wherein the first transistor is coupled to a floating diffusion region.

14. The image sensor of claim 13, wherein the floating diffusion region is coupled to a second transistor, the second transistor comprising a gate and a source/drain region coupled to the power supply.

15. The image sensor of claim 5, wherein at least one first transistor is an anti-blooming transistor.

16. The image sensor of claim 5, wherein at least a portion of the third group is between the second group and the first group.

17. The image sensor of claim 5, further comprising a fourth group of pixel cells each configured such that an output signal of each fourth group pixel cell is discarded.

18. The image sensor of claim 17, wherein at least a portion of the third group is between the second group and the first group, and wherein at least a portion of the fourth group is between the second group and at least a portion of the third group.

19. The image sensor of claim 5, wherein the pixel cells are arranged in columns and rows, and wherein pixel cells of the second and third groups are arranged in a plurality of respective rows adjacent the first group and a plurality of respective columns adjacent the first group.

20. The image sensor of claim 19, wherein there are between approximately 2 and approximately 20 rows in the third group, and wherein there are between approximately 2 and approximately 20 columns in the third group.

21. The image sensor of claim 19, wherein the pixel cells of the second group are arranged in a plurality of adjoining rows and a plurality of adjoining columns, and wherein at least a portion of the pixel cells of the third group are arranged in a plurality of rows between the plurality of rows of the second group and the first group and a plurality of columns between the plurality of columns of the second group and the first group.

22. The image sensor of claim 21, wherein the plurality of rows of the third group flank the plurality of rows of the second group, and wherein the plurality of columns of the third group flank the plurality of columns of the second group.

23. An image sensor comprising:

an array of pixel cells, the array comprising first, second, and third groups of pixel cells, the first group for receiving light, the second and third groups being shielded from light, at least a portion of the third group being located between the first and second groups, each pixel cell of the second group configured to output a black reference signal for determining a black level of the array, and each pixel cell of the third group comprising;

a photo-conversion device; and

at least one first transistor connected to the photo-conversion device for dissipating charge therefrom, each transistor connected to the photo-conversion device having a gate coupled to a power supply voltage.

24. An image sensor comprising:

an array of pixel cells, the array comprising first, second, third and fourth groups of pixel cells, the first group for receiving light, the second, third, and fourth groups being shielded from light, at least a portion of each of the third and fourth groups being located between the first and second groups, each pixel cell of the second group configured to output a black reference signal for determining a black level of the array, each pixel cell of the third group configured such that, during operation, an output from the third group is discarded, and each pixel cell of the fourth group comprising a photo-conversion device and configured to drain charge collected in the photo-conversion device out of the fourth group pixel cell.

25. A processor system, the system comprising:

(i) a processor; and

(ii) an image sensor coupled to the processor, the image sensor comprising;

an array of pixel cells, each pixel cell comprising a photo-conversion device, the array comprising first second and third groups of pixel cells, the first group for receiving light, the second and third groups shielded from light, each pixel cell of the second group configured to output a black reference signal for determining a black level of the array and each pixel cell of the third group comprising at least one first transistor coupled to the photo-conversion device for dissipating charge therefrom, each transistor coupled to the photo-conversion device having a gate coupled to a power supply voltage.

26. A method of operating an image sensor having an array of pixel cells, the method comprising the acts of:

collecting charge in response to light within a first group of pixel cells;

preventing light from reaching photo-conversion devices within at least second and third groups of pixel cells;

isolating the second group from the first group using the third group, at least a portion of the third group being located between the first and second groups;

the act of isolating comprising operating at least a portion of the third group by;

collecting charge in the photo-conversion devices;

continuously operating a gate of each transistor coupled to the photo-conversion devices, each transistor coupled to the photo-conversion devices being a first transistor;

draining the charge from the photo-conversion devices; and

determining a black level for the array based on the output signals of the second group.

27. The method of claim 26, wherein the act of draining the charge comprises draining the charge to a power supply voltage rail coupled to a source/drain region of each first transistor.

28. The method of claim 26, wherein the act of continuously operating the gate of each first transistor comprises applying a power supply voltage to the gate of each first transistor.

29. The method of claim 26, wherein within pixel cells of the third group at least one first transistor is coupled to a floating diffusion region, and wherein the act of isolating further comprises continuously operating a gate of a second transistor coupled to the floating diffusion region.

30. The method of claim 29, wherein the act of draining the charge comprises draining the charge to a power supply voltage rail coupled to a source/drain region of the second transistor.

31. The method of claim 26, wherein the pixel cells of the third group comprise a second transistor coupled to a column line;

and wherein the act of isolating further comprises applying a ground voltage to a gate of the second transistor.

32. The method of claim 26, further comprising the act of preventing light from reaching photo-conversion devices within a fourth group of pixel cells, wherein the act of isolating further comprises isolating the second group from the first group using the fourth group, at least a portion of the fourth group being located between the first and second groups, and discarding an output from each pixel cell of the fourth group.