Semiconductor device

• US 8,411,480 B2
• Filed: 04/08/2011
• Issued: 04/02/2013
• Est. Priority Date: 04/16/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Nagatsuka, Shuhei, Kato, Kiyoshi, Matsuzaki, Takanori, Inoue, Hiroki
• Primary Examiner(s): Ho, Hoal V
• Assistant Examiner(s): HUERTA, PABLO S
• Application Number:
  US13/082,464
• Publication Number:
  US 20110255325A1
• Time in Patent Office: 725 Days
• Field of Search: 365/72
• US Class Current: 365/72
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object is to provide a semiconductor device having a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device includes a memory cell including a widegap semiconductor, for example, an oxide semiconductor. The memory cell includes a writing transistor, a reading transistor, and a selecting transistor. Using a widegap semiconductor, a semiconductor device capable of sufficiently reducing the off-state current of a transistor included in a memory cell and holding data for a long time can be provided.

Claims

1. A semiconductor device comprising:

a write word line;

a read word line;

a bit line;

a source line;

a signal line;

a memory cell comprising;

a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region;

a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region; and

a third transistor comprising a third gate electrode, a third source electrode, a third drain electrode, and a third channel formation region;

a first driver circuit comprising a delay circuit electrically connected to the signal line; and

a second driver circuit,

wherein the first channel formation region comprises a semiconductor material different from a semiconductor material of the second channel formation region,

wherein the first gate electrode and the second drain electrode are electrically connected to each other,

wherein the first drain electrode and the third source electrode are electrically connected to each other,

wherein the source line is electrically connected to the first source electrode,

wherein the first driver circuit is electrically connected to the third drain electrode through the bit line and electrically connected to the second source electrode through the delay circuit and the signal line, and

wherein the second driver circuit is electrically connected to the third gate electrode through the read word line and electrically connected to the second gate electrode through the write word line.

2. The semiconductor device according to claim 1, further comprising a capacitor comprising a first electrode electrically connected to the first gate electrode and a second electrode electrically connected to the source line.

3. The semiconductor device according to claim 1, further comprising a plurality of memory cells,

wherein the memory cell and the plurality of memory cells are connected in parallel between the bit line and the source line.

4. The semiconductor device according to claim 1, wherein the second channel formation region of the second transistor comprises an oxide semiconductor.

5. The semiconductor device according to claim 1, wherein the third channel formation region comprises a same semiconductor material as the first channel formation region.

6. A semiconductor device comprising:

a write word line;

a read word line;

a bit line;

a source line;

a signal line;

a memory cell comprising;

a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region;

a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region; and

a third transistor comprising a third gate electrode, a third source electrode, a third drain electrode, and a third channel formation region;

a first driver circuit comprising a delay circuit electrically connected to the signal line;

a second driver circuit; and

a potential conversion circuit,

wherein the first channel formation region comprises a semiconductor material different from a semiconductor material of the second channel formation region,

wherein the first gate electrode and the second drain electrode are electrically connected to each other,

wherein the first drain electrode and the third source electrode are electrically connected to each other,

wherein the source line is electrically connected to the first source electrode,

wherein the first driver circuit is electrically connected to the third drain electrode through the bit line and electrically connected to the second source electrode through the delay circuit and the signal line,

wherein the second driver circuit is electrically connected to the third gate electrode through the read word line and electrically connected to the second gate electrode through the write word line, and

wherein the potential conversion circuit is configured to output a potential higher than a potential inputted into the potential conversion circuit to the second driver circuit.

7. The semiconductor device according to claim 6, wherein the second driver circuit comprises a step-up level shifter electrically connected to the potential conversion circuit and the write word line.

8. The semiconductor device according to claim 6, further comprising a capacitor comprising a first electrode electrically connected to the first gate electrode and a second electrode electrically connected to the source line.

9. The semiconductor device according to claim 6, further comprising a plurality of memory cells,

wherein the memory cell and the plurality of memory cells are connected in parallel between the bit line and the source line.

10. The semiconductor device according to claim 6, wherein the second channel formation region of the second transistor comprises an oxide semiconductor.

11. The semiconductor device according to claim 6, wherein the third channel formation region comprises a same semiconductor material as the first channel formation region.