Three-stage architecture for adaptive clock recovery

• US 8,411,705 B2
• Filed: 03/24/2010
• Issued: 04/02/2013
• Est. Priority Date: 01/06/2010
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Bedrosian, P. Stephan
• Primary Examiner(s): Yao, Kwang B
• Assistant Examiner(s): DUDA, ADAM K
• Application Number:
  US12/730,286
• Publication Number:
  US 20110164627A1
• Time in Patent Office: 1,105 Days
• Field of Search: 370/231, 370/235, 370/252, 370/253, 370/395, 370/395.6, 370/395.62, 370/474, 370503-520, 375/354, 375/356, 375/371, 375/373, 375/376
• US Class Current: 370/503
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04J 3/0661 using timestamps
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging

Abstract

An adaptive clock recovery (ACR) system has a first closed-loop control processor (e.g., a first proportional-integral (PI) processor) that processes an input phase signal indicative of jittery packet arrival times to generate a mean phase reference. The input phase signal is compared to the mean phase reference to generate delay-offset values that are indicative of the delay-floor corresponding to the packet arrival times. The mean phase reference and the delay-offset values are used to generate offset-compensated phase values corresponding to the delay-floor. The ACR system also has a second closed-loop control processor (e.g., a second PI processor) that smoothes the offset-compensated phase values to generate an output phase signal that can be used to generate a relatively phase stable recovered clock signal, even during periods of varying network load that adversely affect the uniformity of the packet arrival times.

Claims

1. An adaptive clock recovery (ACR) system for a receiver, the ACR system comprising:

a first closed-loop control processor that generates a reference phase signal from an input phase signal representing packet delay values corresponding to arrival times of packets at the receiver;

a delay-offset estimation component, that compares the input phase signal to the reference phase signal to generate a delay-offset estimate signal representative of a phase offset for the packet arrival times relative to the reference phase signal, wherein the phase offset is one of (i) a delay-floor phase offset and (ii) an established phase offset;

a delay-offset compensation component that generates a delay-offset-compensated phase signal based on the reference phase signal and the delay-offset estimate signal; and

a second closed-loop control processor that generates, from the delay-offset-compensated phase signal, an output phase signal, that can be used to generate a recovered clock signal.

2. The ACR system of claim 1, wherein each of the first and second closed-loop control processors is a digital proportional-integral (PI) processor.

3. The ACR system of claim 1, wherein the second closed-loop control processor has a bandwidth that is greater than a bandwidth of the first closed-loop control processor.

4. The ACR system of claim 3, wherein the bandwidth of the second closed-loop control processor is at least twice the bandwidth of the first closed-loop control processor.

5. The ACR system of claim 1, wherein the second closed-loop control processor frequency filters to smooth phase discontinuities in the delay-offset-compensated phase signal.

6. The ACR system of claim 1, wherein the delay-offset estimation component determines a delay-offset value for each packet and generates the delay-offset estimate signal by identifying a largest delay-offset value within a sliding window of packets.

7. The ACR system of claim 6, wherein a size of the sliding window used to identify the largest delay-offset value is at least 40 times smaller than a time constant of the first closed-loop control processor.

8. The ACR system of claim 1, wherein:

each of the first and second closed-loop control processors is a digital proportional-integral (PI) processor;

the second closed-loop control processor has a bandwidth that is greater than a bandwidth of the first closed-loop control processor;

the second closed-loop control processor frequency filters to smooth phase discontinuities in the delay-offset-compensated phase signal; and

the delay-offset estimation component determines a delay-offset value for each packet and generates the delay-offset estimate signal by identifying a largest delay-offset value within a sliding window of packets.

9. The ACR system of claim 8, wherein the bandwidth of the second closed-loop control processor is at least twice the bandwidth of the first closed-loop control processor.

10. The ACR system of claim 8, wherein a size of the sliding window used to identify the largest delay-offset value is at least 40 times smaller than a time constant of the first closed-loop control processor.

18. The ACR system of claim 1, wherein the phase offset is a delay-floor phase offset.

19. The ACR system of claim 1, wherein the phase offset is an established phase offset.

11. A receiver-implemented method for recovering a clock signal in a packet system, the method comprising:

the receiver generating a reference phase signal, from an input phase signal representing packet delay values corresponding to arrival times of packets at a receiver;

the receiver comparing the input phase signal to the reference phase signal to generate a delay-offset estimate signal representative of a phase offset for the packet arrival times relative to the reference phase signal, wherein the phase offset is one of (i) a delay-floor phase offset and (ii) an established phase offset;

the receiver generating a delay-offset-compensated phase signal based on the reference phase signal and the delay-offset estimate signal; and

the receiver generating, from the delay-offset-compensated phase signal, an output phase signal that can be used to generate a recovered clock signal.

12. The receiver-implemented method of claim 11, wherein each of the first and second closed-loop control processors is a digital proportional-integral (PI) processor.

13. The receiver-implemented method of claim 11, wherein the second closed-loop control processor has a bandwidth that is greater than a bandwidth of the first closed-loop control processor.

14. The receiver-implemented method of claim 11, wherein the second closed-loop control processor frequency filters to smooth phase discontinuities in the delay-offset-compensated phase signal.

15. The receiver-implemented method of claim 11, wherein the delay-offset estimation component determines a delay-offset value for each packet and generates the delay-offset estimate signal by identifying a largest delay-offset value within a sliding window of packets.

16. The receiver-implemented method of claim 11, wherein the phase offset is a delay-floor phase offset.

17. The receiver-implemented method of claim 11, wherein the phase offset is an established phase offset.