Digital predistorter for variable supply amplifier

• US 8,411,792 B2
• Filed: 08/03/2010
• Issued: 04/02/2013
• Est. Priority Date: 08/05/2009
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Pinon, Vincent
• Primary Examiner(s): Torres, Juan A
• Application Number:
  US12/849,270
• Publication Number:
  US 20110032032A1
• Time in Patent Office: 973 Days
• Field of Search: 375/297
• US Class Current: 375/297
• CPC Class Codes: H03F 1/0233 by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3294 Acting on the real and imaginary components of the input signal

Abstract

An adaptive predistorter for applying a predistortion gain to an input signal to be amplified by a power amplifier having a variable supply voltage, the predistorter including: a predistortion gain block adapted to apply a complex gain to a complex input signal; a first table implemented in a first memory and including a 2-dimensional array of cells storing complex gain values, the first table adapted to output the complex gain values based on an amplitude of the input signal and the value of the variable supply voltage of the power amplifier; and a second table implemented in a second memory and including a 2-dimensional array of cells storing gain update values for updating the complex gain values of the first table, the gain update values being generated based on an output of the power amplifier.

Claims

1. An adaptive predistorter for applying a predistortion gain to an input signal to be amplified by a power amplifier having a variable supply voltage, the predistorter comprising:

a predistortion gain block adapted to apply a complex gain to a complex input signal;

a first table implemented in a first memory and comprising a 2-dimensional array of cells storing complex gain values, the first table adapted to output said complex gain values based on an amplitude of the input signal and the value of the variable supply voltage of the power amplifier; and

a second table implemented in a second memory and comprising a 2-dimensional array of cells storing gain update values for updating the complex gain values of the first table, the gain update values being generated based on an output signal of said power amplifier.

2. The predistorter of claim 1, wherein the complex gain values in said first table are in Cartesian format, and wherein said gain update values in said second table are complex values also in Cartesian format.

3. The predistorter of claim 1, further comprising a table update block adapted to generate updated complex gain values based on said complex gain values of the first table and the gain update values of the second table.

4. The predistorter of claim 3, wherein the table update block is adapted to update the complex gain values based on the following calculation for each address in the first table:

G′

x,y=Gx,y·

G2x,y

where G′

x,y is the new complex gain value corresponding to address x,y of the first table, Gx,y is the previous complex gain value at address x,y of the first table and G2x,y is the gain update value at address x,y of the second table.

5. The predistorter of claim 1, further comprising a feedback control block adapted to generate said gain update values based on the complex input signal, the output signal of said power amplifier and a previous gain update value stored in said second table.

6. The predistorter of claim 5, wherein a first order infinite impulse response filtering function is applied when generating said gain update values, based on the following calculation:

G2′

x,y=G2x,y+(G2x,y−

m)α

wherein G2′

x,y is a new gain update value to be stored at address x,y in the second table, G2x,y is the previous gain update value at address x,y in the second table, m is a gain ratio equal to the complex input signal divided by the output signal of the power amplifier, and α

is a constant.

7. The predistorter of claim 1, wherein the first and second tables are each addressed by a column address based on the variable supply voltage and a row address, wherein the row address of the first table is based on the amplitude of the complex input signal and the row address of the second table is based on the amplitude of the output signal of the power amplifier.

8. The predistorter of claim 7, wherein the row address input to the first table is equal to:

(AMIN[n]|/VS[n]),

and the row address input (y2[n]) to the second table is equal to;

(AMOUT[n]/VS[n]),

wherein AMIN[n] is the amplitude of the complex input signal and AMOUT[n] is the amplitude of the complex output signal of the power amplifier converted into digital format and VS[n] is the variable supply voltage converted into digital format.

9. The predistorter of claim 7, wherein the row address input (y1[n]) to the first table is equal to:

(AMIN[n]/VS[n])2,

and the row address input (y2[n]) to the second table is equal to;

(AMOUT[n]/VS[n])2,

wherein AMIN[n] is the amplitude of the complex input signal and AMOUT[n] is the amplitude of the complex output signal of the power amplifier converted into digital format and VS[n] is the variable supply voltage converted into digital format.

10. The predistorter of claim 1, wherein roles of the first and second tables are exchanged periodically.

11. An amplification circuit arrangement comprising:

the predistorter of claim 1 for applying a predistortion gain to an input signal;

a first RF converter for converting the predistorted input signal to an analog signal at a transmission frequency; and

a power amplifier for amplifying the analog signal, the power amplifier being powered by a variable supply voltage.

12. An electronic device comprising:

modulation circuitry for generating the complex input signal; and

the amplification circuit arrangement of claim 11.

13. A method of applying a predistortion gain to a complex input signal to be amplified by a power amplifier having a variable supply voltage, comprising:

applying to the complex input signal, by a predistortion gain block, complex gain values extracted from a first table comprising a 2-dimensional array of cells storing complex gain values, said complex gain values being extracted based on an amplitude of the complex input signal, and a value of the variable supply voltage of the power amplifier; and

accumulating in a 2-dimensional array of a second table gain update values for updating the complex gain values of the first table, the gain update values being generated based on an output signal of said power amplifier.

14. The method of claim 13, further comprising periodically switching the roles of said first and second tables such that said first table is used for accumulating a 2-dimensional array of gain update values generated based on an output signal of said power amplifier, and the second table is used for providing said complex gain values.

15. A digital predistorter comprising:

a predistortion gain block configured to apply a complex gain value to a complex input signal to be amplified by a power amplifier and to output a predistorted signal to the power amplifier;

a first table configured to store complex gain values and to output a selected complex gain value to the predistortion gain block based on an amplitude of the input signal and a value of a variable supply voltage of the power amplifier; and

a second table configured to store gain update values for updating the complex gain values in the first table based on an output signal of the power amplifier.

16. A digital predistorter as defined in claim 15, wherein the first and second tables are implemented in first and second memory arrays, respectively.

17. A digital predistorter as defined in claim 15, wherein the first table comprises a two-dimensional memory array that is addressed based on a value of the variable supply voltage and a value of the input signal amplitude.

18. A digital predistorter as defined in claim 15, further comprising a table update block configured to generate updated complex gain values based on the complex gain values in the first table and the gain update values in the second table.

19. A digital predistorter as defined in claim 18, wherein the table update block is configured to update the complex gain values based on the following calculation for each address in the first table:

G′

x,y=Gx,y·

G2x,y

where G′

x,y is the new complex gain value corresponding to address x,y of the first table, Gx,y is the previous complex gain value at address x,y of the first table and G2x,y is the gain update value at address x,y of the second table.

20. A digital predistorter as defined in claim 15, further comprising a feedback control block configured to generate the gain update values based on the complex input signal, the output signal of the power amplifier and a previous gain update value stored in the second table.

21. A digital predistorter as defined in claim 20, wherein a first order infinite impulse response filtering function is applied when generating the gain update values, based on the following calculation:

G2′

x,y=G2x,y+(G2x,y−

m)α

wherein G2′

x,y is a new gain update value to be stored at address x,y in the second table, G2x,y is the previous gain update value at address x,y in the second table, m is a gain ratio equal to the complex input signal divided by the output signal of the power amplifier, and α

is a constant.

22. A digital predistorter as defined in claim 15, wherein the first and second tables are each addressed by a column address based on the variable supply voltage, and wherein a row address of the first table is based on the amplitude of the complex input signal and a row address of the second table is based on the amplitude of the output signal of the power amplifier.

23. A digital predistorter as defined in claim 15, further comprising multiplexers configured to periodically switch roles of the first and second tables.

24. A digital predistortion method comprising:

storing, in a first table, complex gain values;

applying, by a predistortion gain block, to a complex input signal to be amplified by a power amplifier, a complex gain value selected from the first table based on an amplitude of the input signal and a value of a variable power supply of the power amplifier;

storing, in a second table, gain update values based on an output signal of the power amplifier; and

updating, by a table update block, the complex gain values in the first table based on the gain update values in the second table.

25. A digital predistortion method as defined in claim 24, further comprising generating, by a feedback control block, the gain update values based on the complex input signal, the output signal of the power amplifier and a previous gain update value stored in the second table.

26. A digital predistortion method as defined in claim 24, further comprising periodically switching roles of the first and second tables.