Multi-operand floating point operations in a programmable integrated circuit device

• US 8,412,756 B1
• Filed: 09/11/2009
• Issued: 04/02/2013
• Est. Priority Date: 09/11/2009
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): SUN, SCOTT C
• Application Number:
  US12/557,952
• Time in Patent Office: 1,299 Days
• Field of Search: None
• US Class Current: 708/201
• CPC Class Codes: G06F 7/485 Adding; Subtracting G06F7/4833, G06F7/4836 take precedence
• CPC Class Codes: G06F 7/5095 word-serial, i.e. with an accumulator-register

Abstract

A programmable logic device is programmed to add a plurality N of unnormalized numbers at once. Because the inputs are not normalized, they could all have different exponents. The largest exponent of the N exponents is found, and for each of the inputs, its mantissa is right-shifted at by the difference between the largest exponent and the exponent of that particular input. The N shifted mantissas are combined, optionally with sign data, in an (N+1):2 compressor to provide carry and save vectors which may be combined in a carry-propagate adder. Numbers may converted back to normalized form at the end of the operation. If necessary to avoid data loss, a number may be normalized after an intermediate step.

Claims

1. A method of configuring a programmable integrated circuit device to perform floating point addition operations on more than two numbers, each of said numbers being represented by a respective mantissa and a respective exponent, said method comprising:

configuring logic of said programmable integrated circuit device to determine a largest exponent of said respective exponent of said more than two numbers, and to subtract each respective said exponent from said largest exponent to determine a respective shifting amount, and to select said largest exponent as a resultant exponent;

configuring logic of said programmable integrated circuit device to shift each respective mantissa of said more than two numbers by said respective shifting amount;

configuring a compressor in said programmable integrated circuit device to simultaneously combine said more than two shifted mantissas into a carry vector and a save vector; and

configuring a carry-propagate adder in said programmable integrated circuit device to combine said carry vector and said save vector.

2. The method of claim 1 wherein:

said configuring logic of said programmable integrated circuit device to determine a largest exponent comprises configuring logic of said programmable integrated circuit device to perform a binary sort.

3. The method of claim 1 further comprising:

configuring logic of said programmable integrated circuit device to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount.

4. The method of claim 3 wherein:

configuring logic of said programmable integrated circuit device to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount comprises configuring logic of said programmable integrated circuit device to determine said left-shift amount by counting leading zeroes in said resultant mantissa when said resultant mantissa represents an unsigned number or a positive signed number, and by counting leading ones in said resultant mantissa when said resultant mantissa represents a negative signed number.

5. The method of claim 3 further comprising configuring logic of said programmable integrated circuit device to round said normalized resultant mantissa and said reduced resultant exponent to produce a final mantissa and a final exponent.

6. The method of claim 1 wherein:

said floating-point addition operations include one or both of negative addends and subtraction operations; and

said numbers are unsigned numbers having mantissas and separate sign bits;

said method further comprising;

configuring logic of said programmable integrated circuit device to count each of said numbers having a sign bit equal to 1, representing a negative addend or a subtraction, for input to said compressor;

configuring logic of said programmable integrated circuit device to invert said mantissas of any negative addend, and any minuend in any subtraction operation, for input to said compressor.

7. The method of claim 1 wherein:

said floating-point addition operations include one or both of negative addends and subtraction operations; and

said numbers are signed numbers having sign bits as part of their mantissas;

said method further comprising;

configuring logic of said programmable integrated circuit device to count subtraction control bits associated with said numbers for input to said compressor.

8. A programmable integrated circuit device configurable to perform floating point addition operations on more than two numbers, each of said numbers being represented by a respective mantissa and a respective exponent, said programmable integrated circuit device comprising:

programmable logic configurable to determine a largest exponent of said respective exponent of said more than two numbers, and to subtract each respective said exponent from said largest exponent to determine a respective shifting amount, and to select said largest exponent as a resultant exponent;

programmable logic configurable to shift each respective mantissa of said plurality of numbers by said respective shifting amount;

programmable logic configurable as a compressor to simultaneously combine said plurality of shifted mantissas into a carry vector and a save vector; and

programmable logic configurable to combine said carry vector and said save vector.

9. The device of claim 8 wherein said programmable logic configurable to combine said carry vector and said save vector comprises a fixed carry-propagate adder.

10. The device of claim 8 wherein said programmable logic configurable to combine said carry vector and said save vector comprises logic configurable as a carry-propagate adder.

11. The device of claim 8 wherein said programmable logic configurable to determine a largest exponent comprises programmable logic configurable to perform a binary sort.

12. The device of claim 8 further comprising programmable logic configurable to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount.

13. The device of claim 12 wherein said logic configurable to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount comprises logic configurable to determine said left-shift amount by counting leading zeroes in said resultant mantissa when said resultant mantissa represents an unsigned number or a positive signed number, and by counting leading ones in said resultant mantissa when said resultant mantissa represents a negative signed number.

14. The device of claim 12 further comprising logic configurable to round said normalized resultant mantissa and said reduced resultant exponent to produce a final mantissa and a final exponent.

15. The device of claim 8 wherein:

said floating-point addition operations include one or both of negative addends and subtraction operations; and

said numbers are unsigned numbers having mantissas and separate sign bits;

said device further comprising;

logic configured to count each of said numbers having a sign bit equal to 1, representing a negative addend or a subtraction, for input to said compressor;

logic configured to invert said mantissas of any negative addend, and any minuend in any subtraction operation, for input to said compressor.

16. The device of claim 8 wherein:

said floating-point addition operations include one or both of negative addends and subtraction operations; and

said numbers are signed numbers having sign bits as part of their mantissas;

said device further comprising;

logic configured to count subtraction control bits associated with said numbers for input to said compressor.

17. A non-transitory machine-readable data storage medium encoded with machine-executable instructions for configuring a programmable integrated circuit device to perform floating point addition operations on a more than two numbers, each of said numbers being represented by a respective mantissa and a respective exponent, said instructions comprising:

instructions to configure logic of said programmable integrated circuit device to determine a largest exponent of said respective exponent of said more than two numbers, and to subtract each respective said exponent from said largest exponent to determine a respective shifting amount, and to select said largest exponent as a resultant exponent;

instructions to configure logic of said programmable integrated circuit device to shift each respective mantissa of said more than two numbers by said respective shifting amount;

instructions to configure a compressor in said programmable integrated circuit device to simultaneously combine said more than two shifted mantissas into a carry vector and a save vector; and

instructions to configure a carry-propagate adder in said programmable integrated circuit device to combine said carry vector and said save vector.

18. The non-transitory machine-readable data storage medium of claim 17 wherein said instructions to configure logic of said programmable integrated circuit device to determine a largest exponent comprise instructions to configure logic of said programmable integrated circuit device to perform a binary sort.

19. The non-transitory machine-readable data storage medium of claim 17 wherein said instructions further comprise instructions to configure logic of said programmable integrated circuit device to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount.

20. The non-transitory machine-readable data storage medium of claim 19 wherein said instructions to configure logic of said programmable integrated circuit device to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount comprise instructions to configure logic of said programmable integrated circuit device to determine said left-shift amount by counting leading zeroes in said resultant mantissa when said resultant mantissa represents an unsigned number or a positive signed number, and by counting leading ones in said resultant mantissa when said resultant mantissa represents a negative signed number.

21. The non-transitory machine-readable data storage medium of claim 19 wherein said instructions further comprise instructions to configure logic of said programmable integrated circuit device to round said normalized resultant mantissa and said reduced resultant exponent to produce a final mantissa and a final exponent.

22. Circuitry for performing floating point addition operations on more than two numbers, each of said numbers being represented by a respective mantissa and a respective exponent, said circuitry comprising:

logic to determine a largest exponent of said respective exponent of said more than two numbers, and to subtract each respective said exponent from said largest exponent to determine a respective shifting amount, and to select said largest exponent as a resultant exponent;

logic to shift each respective mantissa of said more than two numbers by said respective shifting amount;

a compressor to simultaneously combine said more than two shifted mantissas into a carry vector and a save vector; and

logic to combine said carry vector and said save vector.

23. The circuitry of claim 22 wherein said logic to combine said carry vector and said save vector comprises a carry-propagate adder.

24. The circuitry of claim 22 wherein said logic to determine a largest exponent comprises binary sort logic.

25. The circuitry of claim 22 further comprising logic to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount.

26. The circuitry of claim 25 wherein said logic to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount comprises count-leading-zeroes logic to count leading zeroes in said resultant mantissa to determine said left-shift amount when said resultant mantissa represents an unsigned number or a positive signed number, and count-leading-ones logic to count leading ones in said resultant mantissa to determine said left-shift amount when said resultant mantissa represents a negative signed number.

27. The circuitry of claim 25 further comprising logic to round said normalized resultant mantissa and said reduced resultant exponent to produce a final mantissa and a final exponent.

28. The circuitry of claim 22 wherein:

said floating-point addition operations include one or both of negative addends and subtraction operations; and

said numbers are unsigned numbers having mantissas and separate sign bits;

said circuitry further comprising;

logic to count each of said numbers having a sign bit equal to 1, representing a negative addend or a subtraction, for input to said compressor; and

logic to invert said mantissas of any negative addend, and any minuend in any subtraction operation, for input to said compressor.

29. The circuitry of claim 22 wherein:

said floating-point addition operations include one or both of negative addends and subtraction operations; and

said numbers are signed numbers having sign bits as part of their mantissas;

said circuitry further comprising;

logic to count subtraction control bits associated with said numbers for input to said compressor.